diff options
| author | Simon Glass <sjg@chromium.org> | 2017-03-31 08:40:25 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-04-05 13:59:20 -0400 |
| commit | 088454cde245b4d431ce0181be8b3cbceea059d6 (patch) | |
| tree | ec86ebe66961c9b06ab4b39ec83fd81d4a86e9be /board/liebherr | |
| parent | 52c411805c090999f015df8bdf8016fb684746d0 (diff) | |
| download | u-boot-088454cde245b4d431ce0181be8b3cbceea059d6.tar.gz | |
board_f: Drop return value from initdram()
At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/liebherr')
| -rw-r--r-- | board/liebherr/lwmon5/sdram.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/board/liebherr/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c index 1932e06fd6..f7251e567f 100644 --- a/board/liebherr/lwmon5/sdram.c +++ b/board/liebherr/lwmon5/sdram.c @@ -25,6 +25,8 @@ #include <asm/ppc440.h> #include <watchdog.h> +DECLARE_GLOBAL_DATA_PTR; + /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory * region. Right now the cache should still be disabled in U-Boot because of the @@ -145,7 +147,7 @@ static void program_ecc(u32 start_address, * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -phys_size_t initdram(void) +int initdram(void) { /* CL=4 */ mtsdram(DDR0_02, 0x00000000); @@ -241,5 +243,7 @@ phys_size_t initdram(void) */ set_mcsr(get_mcsr()); - return (CONFIG_SYS_MBYTES_SDRAM << 20); + gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20; + + return 0; } |