driver/ddr: Add support for setting timing in hws_topology_map

The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
  HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
                    from the number of CSs
  HWS_TIM_1T      - enforce 1t
  HWS_TIM_2T      - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 2 insertions, 1 deletions

diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index f0efb53447..32168d3576 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -53,7 +53,8 @@ static struct hws_topology_map ddr_topology_map = {
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_533,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/
 	BUS_MASK_32BIT			/* Busses mask */
 };