diff options
| author | Tom Rini <trini@konsulko.com> | 2015-05-05 14:57:23 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-05-05 14:57:23 -0400 |
| commit | d81572c272d4b0980fb9b8a02e1357090b002398 (patch) | |
| tree | 4b2f774d628ab51944f0ba1ff83c15ef6b082a0f /board/freescale/t208xrdb | |
| parent | 1131d4e22cf8f13d0dabaad7f1b84d9baffdfbd6 (diff) | |
| parent | 8b0044ff5942943eaa49935f49d5006b346a60f8 (diff) | |
| download | u-boot-d81572c272d4b0980fb9b8a02e1357090b002398.tar.gz | |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/t208xrdb')
| -rw-r--r-- | board/freescale/t208xrdb/cpld.h | 3 | ||||
| -rw-r--r-- | board/freescale/t208xrdb/t2080_rcw.cfg | 5 | ||||
| -rw-r--r-- | board/freescale/t208xrdb/t208xrdb.c | 7 |
3 files changed, 14 insertions, 1 deletions
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index 3f1533888d..9bd5247563 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 #define CPLD_BOOT_SEL 0x80 + +/* RSTCON Register */ +#define CPLD_RSTCON_EDC_RST 0x04 diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg index 59025eaf1e..8096ff9f37 100644 --- a/board/freescale/t208xrdb/t2080_rcw.cfg +++ b/board/freescale/t208xrdb/t2080_rcw.cfg @@ -10,7 +10,10 @@ aa55aa55 010e0100 #For T2080 v1.1 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s -1206001b 15000000 00000000 00000000 +#1206001b 15000000 00000000 00000000 + +#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s +1207001b 15000000 00000000 00000000 66150002 00000000 e8104000 c1000000 00800000 00000000 00000000 000307fc 00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index ad393dfc5c..0c2c1c565b 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -107,6 +107,13 @@ unsigned long get_board_ddr_clk(void) int misc_init_r(void) { + u8 reg; + + /* Reset CS4315 PHY */ + reg = CPLD_READ(reset_ctl); + reg |= CPLD_RSTCON_EDC_RST; + CPLD_WRITE(reset_ctl, reg); + return 0; } |