diff options
| author | York Sun <york.sun@nxp.com> | 2017-05-17 10:19:35 -0700 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-06-12 11:30:00 -0700 |
| commit | 3913191c8a6b8309d08fab803ed72a43d3b5a5fb (patch) | |
| tree | a04f8cd8cd5e5750b392c0ba161cd79a9c5d9b1e /board/freescale/mpc8540ads/tlb.c | |
| parent | 8cb3ce64f936f5dedbcfc1935c5caf31bb682474 (diff) | |
| download | u-boot-3913191c8a6b8309d08fab803ed72a43d3b5a5fb.tar.gz | |
powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS
Drop support for these two legacy boards.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/mpc8540ads/tlb.c')
| -rw-r--r-- | board/freescale/mpc8540ads/tlb.c | 95 |
1 files changed, 0 insertions, 95 deletions
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c deleted file mode 100644 index d5ee791da6..0000000000 --- a/board/freescale/mpc8540ads/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); |