diff options
| author | Alison Wang <alison.wang@nxp.com> | 2018-10-16 16:19:22 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-12-06 14:37:19 -0800 |
| commit | f668c52033548ad1d6430ebd29cdda713819415f (patch) | |
| tree | f9513dd7260fb9882dd1293bcfe6ebb46e962a26 /board/freescale/ls1021aqds/ls1021aqds.c | |
| parent | 71037f62ff3355e268627dc142594f8b974703f6 (diff) | |
| download | u-boot-f668c52033548ad1d6430ebd29cdda713819415f.tar.gz | |
arm: ls1021a: Add timer_init() in board_init_f for SPL
I2C is used to access DDR SPD in the DDR initialization for SPL. In
i2c_write process, get_timer() will be called. In board_init_f for SPL,
timer_init() is not called before. The system counter is not enabled and
the counter frequency is not set to 12.5MHz in SPL. The parameters for
do_div() are zero too.
It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in
default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its
own set of libgcc functions. As the parameters for do_div() are zero,
__div0 will be called. Then the processor will stay in an endless loop
after calling hang().
This patch will add timer_init() in board_init_f for SPL and fix a
series of issues it caused.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls1021aqds/ls1021aqds.c')
| -rw-r--r-- | board/freescale/ls1021aqds/ls1021aqds.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index c828dacf9e..c08be1ee46 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -244,6 +244,7 @@ void board_init_f(ulong dummy) if (major == SOC_MAJOR_VER_1_0) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + timer_init(); dram_init(); /* Allow OCRAM access permission as R/W */ |