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| author | Ludwig Zenz <lzenz@dh-electronics.de> | 2018-07-05 09:23:46 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2018-07-23 11:01:41 +0200 |
| commit | 3d81584d40877f95a381355438e5694253f5fa9b (patch) | |
| tree | 75f11b44d541f62f97e17e2b741635a794b07477 /board/dhelectronics | |
| parent | 3a68ad49352ba1d33820e5ece4decd3ddb7c0287 (diff) | |
| download | u-boot-3d81584d40877f95a381355438e5694253f5fa9b.tar.gz | |
Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK"
This reverts commit a637fe6f27fd4c19ef9f43a5f871c244581422ac.
The DDR DRAM calibration was enhanced by write leveling correction code.
It can be used with T-topology now.
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Diffstat (limited to 'board/dhelectronics')
| -rw-r--r-- | board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index dffe4ebd45..beda38955e 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -384,6 +384,10 @@ void board_init_f(ulong dummy) &dhcom6sdl_grp_ioregs); mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr); + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_info); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); |