Merge branch '2021-09-02-assorted-platform-and-bugfixes' into next

- Add position independent execution support for ARMv7
- Snapdragon, synquacer, vexpress64 fixes / improvements
- Prevent NEON register use on ARMv8
- Other assorted fixes

3 files changed, 30 insertions, 2 deletions

diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 1d13f542e6..1f0c7ad969 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -1,4 +1,5 @@
-if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO
+if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || \
+	TARGET_VEXPRESS64_BASER_FVP
 
 config SYS_BOARD
 	default "vexpress64"
@@ -7,7 +8,7 @@ config SYS_VENDOR
 	default "armltd"
 
 config SYS_CONFIG_NAME
-	default "vexpress_aemv8a"
+	default "vexpress_aemv8"
 
 config JUNO_DTB_PART
 	string "NOR flash partition holding DTB"
diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS
index 0ba044d7ff..875401ae1b 100644
--- a/board/armltd/vexpress64/MAINTAINERS
+++ b/board/armltd/vexpress64/MAINTAINERS
@@ -14,3 +14,8 @@ JUNO DEVELOPMENT PLATFORM BOARD
 M:	Linus Walleij <linus.walleij@linaro.org>
 S:	Maintained
 F:	configs/vexpress_aemv8a_juno_defconfig
+
+VEXPRESS64 BASER_FVP
+M:	Peter Hoyes <Peter.Hoyes@arm.com>
+S:	Maintained
+F:	configs/vexpress_aemv8r_defconfig
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 2e4260286b..eb4951d07c 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -18,6 +18,7 @@
 #include <dm/platform_data/serial_pl01x.h>
 #include "pcie.h"
 #include <asm/armv8/mmu.h>
+#include <asm/armv8/mpu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,6 +55,27 @@ static struct mm_region vexpress64_mem_map[] = {
 
 struct mm_region *mem_map = vexpress64_mem_map;
 
+static struct mpu_region vexpress64_aemv8r_mem_map[] = {
+	{
+		.start = 0x0UL,
+		.end = 0x7fffffffUL,
+		.attrs = PRLAR_ATTRIDX(MT_NORMAL)
+	}, {
+		.start = 0x80000000UL,
+		.end = 0xffffffffUL,
+		.attrs = PRLAR_ATTRIDX(MT_DEVICE_NGNRNE)
+	}, {
+		.start = 0x100000000UL,
+		.end = 0xffffffffffUL,
+		.attrs = PRLAR_ATTRIDX(MT_NORMAL)
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mpu_region *mpu_mem_map = vexpress64_aemv8r_mem_map;
+
 /* This function gets replaced by platforms supporting PCIe.
  * The replacement function, eg. on Juno, initialises the PCIe bus.
  */