diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2011-11-09 06:15:59 +0000 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-11-10 15:27:15 +0100 |
commit | 701ed16e23c2c9c11ea26ea57e037f7833bb00ba (patch) | |
tree | 167bcbe99a14d50dd9a19b792fb98dabfd9e6980 /board/armltd/integrator/integrator.c | |
parent | 7c045d0bfec1e2990e19d3eb1852839e27270387 (diff) | |
download | u-boot-701ed16e23c2c9c11ea26ea57e037f7833bb00ba.tar.gz |
integrator: make flash writeable on boot
This reconfigures the EBI (External Bus Interface) on the
integrator so that chip select 1, handling the flash memory, is
set to writeable. Without this it is not possible for U-Boot to
access flash memory and it crashes on startup since CFI won't
work properly.
Since this is the first time we use the EBI, we create a header
file for its registers.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'board/armltd/integrator/integrator.c')
-rw-r--r-- | board/armltd/integrator/integrator.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 780218cbe9..dd83ca5c03 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -36,6 +36,7 @@ #include <common.h> #include <netdev.h> #include <asm/io.h> +#include "arm-ebi.h" DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +57,8 @@ void show_boot_progress(int progress) int board_init (void) { + u32 val; + /* arch number of Integrator Board */ #ifdef CONFIG_ARCH_CINTEGRATOR gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; @@ -73,6 +76,18 @@ extern void cm_remap(void); cm_remap(); /* remaps writeable memory to 0x00000000 */ #endif + /* + * The system comes up with the flash memory non-writable and + * configuration locked. If we want U-Boot to be used for flash + * access we cannot have the flash memory locked. + */ + writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); + val = readl(EBI_BASE + EBI_CSR1_REG); + val &= EBI_CSR_WREN_MASK; + val |= EBI_CSR_WREN_ENABLE; + writel(val, EBI_BASE + EBI_CSR1_REG); + writel(0, EBI_BASE + EBI_LOCK_REG); + icache_enable (); return 0; |