diff options
author | Carlo Caione <carlo@endlessm.com> | 2016-06-10 20:18:23 +0200 |
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committer | Tom Rini <trini@konsulko.com> | 2016-06-24 17:23:09 -0400 |
commit | 1e23737df8c3887afd45b3c9842827df168d915b (patch) | |
tree | 74d2cc951264f6e3df9cc4ef5e2ad124da8d7258 /board/amlogic/odroid-c2/odroid-c2.c | |
parent | 4b3ab59d21efc2bcc76628a54f9c368dee23d5fe (diff) | |
download | u-boot-1e23737df8c3887afd45b3c9842827df168d915b.tar.gz |
board: amlogic: Rename folder for Amlogic boards
s/hardkernel/amlogic/ to have a single place for all the amlogic-based
boards.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Diffstat (limited to 'board/amlogic/odroid-c2/odroid-c2.c')
-rw-r--r-- | board/amlogic/odroid-c2/odroid-c2.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c new file mode 100644 index 0000000000..bd72100e09 --- /dev/null +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gxbb.h> +#include <asm/arch/sm.h> +#include <dm/platdata.h> +#include <phy.h> + +#define EFUSE_SN_OFFSET 20 +#define EFUSE_SN_SIZE 16 +#define EFUSE_MAC_OFFSET 52 +#define EFUSE_MAC_SIZE 6 + +int board_init(void) +{ + return 0; +} + +static const struct eth_pdata gxbb_eth_pdata = { + .iobase = GXBB_ETH_BASE, + .phy_interface = PHY_INTERFACE_MODE_RGMII, +}; + +U_BOOT_DEVICE(meson_eth) = { + .name = "eth_designware", + .platdata = &gxbb_eth_pdata, +}; + +int misc_init_r(void) +{ + u8 mac_addr[EFUSE_MAC_SIZE]; + ssize_t len; + + /* Select Ethernet function */ + setbits_le32(GXBB_PINMUX(6), 0x3fff); + + /* Set RGMII mode */ + setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | + GXBB_ETH_REG_0_TX_PHASE(1) | + GXBB_ETH_REG_0_TX_RATIO(4) | + GXBB_ETH_REG_0_PHY_CLK_EN | + GXBB_ETH_REG_0_CLK_EN); + + /* Enable power and clock gate */ + setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); + clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); + + /* Reset PHY on GPIOZ_14 */ + clrbits_le32(GXBB_GPIO_EN(3), BIT(14)); + clrbits_le32(GXBB_GPIO_OUT(3), BIT(14)); + mdelay(10); + setbits_le32(GXBB_GPIO_OUT(3), BIT(14)); + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, + mac_addr, EFUSE_MAC_SIZE); + if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + return 0; +} |