powerpc: remove 4xx support

There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

6 files changed, 0 insertions, 544 deletions

diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig
deleted file mode 100644
index 31ce5f10c6..0000000000
--- a/board/amcc/makalu/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MAKALU
-
-config SYS_BOARD
-	default "makalu"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "makalu"
-
-endif
diff --git a/board/amcc/makalu/MAINTAINERS b/board/amcc/makalu/MAINTAINERS
deleted file mode 100644
index ecd5e19c61..0000000000
--- a/board/amcc/makalu/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MAKALU BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/makalu/
-F:	include/configs/makalu.h
-F:	configs/makalu_defconfig
diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile
deleted file mode 100644
index dcf162ca98..0000000000
--- a/board/amcc/makalu/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= makalu.o cmd_pll.o
-obj-y	+= init.o
diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c
deleted file mode 100644
index f12655bea2..0000000000
--- a/board/amcc/makalu/cmd_pll.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * ehnus: change pll frequency.
- * Wed Sep  5 11:45:17 CST 2007
- * hsun@udtech.com.cn
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <i2c.h>
-
-#ifdef CONFIG_CMD_EEPROM
-
-#define EEPROM_CONF_OFFSET		0
-#define EEPROM_TEST_OFFSET		16
-#define EEPROM_SDSTP_PARAM		16
-
-#define PLL_NAME_MAX			12
-#define BUF_STEP			8
-
-/* eeprom_wirtes 8Byte per op. */
-#define EEPROM_ALTER_FREQ(freq)						\
-	do {								\
-		int __i;						\
-		for (__i = 0; __i < 2; __i++)				\
-			eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR,		\
-				      EEPROM_CONF_OFFSET + __i*BUF_STEP, \
-				      pll_select[freq],			\
-				      BUF_STEP + __i*BUF_STEP);		\
-	} while (0)
-
-#define PDEBUG
-#ifdef	PDEBUG
-#define PLL_DEBUG	pll_debug(EEPROM_CONF_OFFSET)
-#else
-#define PLL_DEBUG
-#endif
-
-typedef enum {
-	PLL_ebc20,
-	PLL_333,
-	PLL_4001,
-	PLL_4002,
-	PLL_533,
-	PLL_600,
-	PLL_666,	/* For now, kilauea can't support */
-	RCONF,
-	WTEST,
-	PLL_TOTAL
-} pll_freq_t;
-
-static const char
-pll_name[][PLL_NAME_MAX] = {
-	"PLL_ebc20",
-	"PLL_333",
-	"PLL_400@1",
-	"PLL_400@2",
-	"PLL_533",
-	"PLL_600",
-	"PLL_666",
-	"RCONF",
-	"WTEST",
-	""
-};
-
-/*
- * ehnus:
- */
-static uchar
-pll_select[][EEPROM_SDSTP_PARAM] = {
-	/* 0: CPU 333MHz EBC 20MHz, for test only */
-	{
-		0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 0: 333 */
-	{
-		0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 1: 400_266 */
-	{
-		0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 2: 400 */
-	{
-		0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 3: 533 */
-	{
-		0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 4: 600 */
-	{
-		0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 5: 666 */
-	{
-		0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	{}
-};
-
-static uchar
-testbuf[EEPROM_SDSTP_PARAM] = {
-	0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-	0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
-};
-
-static void
-pll_debug(int off)
-{
-	int i;
-	uchar buffer[EEPROM_SDSTP_PARAM];
-
-	memset(buffer, 0, sizeof(buffer));
-	eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
-		    buffer, EEPROM_SDSTP_PARAM);
-
-	printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
-	for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
-		printf("%02x ", buffer[i]);
-	printf("\n");
-}
-
-static void
-test_write(void)
-{
-	printf("Debug: test eeprom_write ... ");
-
-	/*
-	 * Write twice, 8 bytes per write
-	 */
-	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
-		      testbuf, 8);
-	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
-		      testbuf, 16);
-	printf("done\n");
-
-	pll_debug(EEPROM_TEST_OFFSET);
-}
-
-int
-do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	char c = '\0';
-	pll_freq_t pll_freq;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
-		if (!strcmp(pll_name[pll_freq], argv[1]))
-			break;
-	}
-
-	switch (pll_freq) {
-	case PLL_ebc20:
-	case PLL_333:
-	case PLL_4001:
-	case PLL_4002:
-	case PLL_533:
-	case PLL_600:
-		EEPROM_ALTER_FREQ(pll_freq);
-		break;
-
-	case PLL_666:		/* not support */
-		printf("Choose this option will result in a boot failure."
-		       "\nContinue? (Y/N): ");
-
-		c = getc(); putc('\n');
-
-		if ((c == 'y') || (c == 'Y')) {
-			EEPROM_ALTER_FREQ(pll_freq);
-			break;
-		}
-		goto ret;
-
-	case RCONF:
-		pll_debug(EEPROM_CONF_OFFSET);
-		goto ret;
-	case WTEST:
-		printf("DEBUG: write test\n");
-		test_write();
-		goto ret;
-
-	default:
-		printf("Invalid options\n\n");
-		return cmd_usage(cmdtp);
-	}
-
-	printf("PLL set to %s, "
-	       "reset the board to take effect\n", pll_name[pll_freq]);
-
-	PLL_DEBUG;
-ret:
-	return 0;
-}
-
-U_BOOT_CMD(
-	pllalter, CONFIG_SYS_MAXARGS, 1,        do_pll_alter,
-	"change pll frequence",
-	"pllalter <selection>      - change pll frequence \n\n\
-	** New freq take effect after reset. ** \n\
-	----------------------------------------------\n\
-	PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	Same as PLL_333	\n\
-	\t	except          \n\
-	\t	EBC: 20 MHz     \n\
-	----------------------------------------------\n\
-	PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 666 MHz  \n\
-	\t	CPU: 333 MHz  \n\
-	\t	PLB: 166 MHz  \n\
-	\t	OPB: 83 MHz   \n\
-	\t	DDR: 83 MHz   \n\
-	------------------------------------------------\n\
-	PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 800 MHz  \n\
-	\t	CPU: 400 MHz  \n\
-	\t	PLB: 133 MHz  \n\
-	\t	OPB: 66  MHz  \n\
-	\t	DDR: 133 MHz  \n\
-	------------------------------------------------\n\
-	PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 800 MHz  \n\
-	\t	CPU: 400 MHz  \n\
-	\t	PLB: 200 MHz  \n\
-	\t	OPB: 100 MHz  \n\
-	\t	DDR: 200 MHz  \n\
-	----------------------------------------------\n\
-	PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 1066 MHz  \n\
-	\t	CPU: 533  MHz  \n\
-	\t	PLB: 177  MHz  \n\
-	\t	OPB: 88   MHz  \n\
-	\t	DDR: 177  MHz  \n\
-	----------------------------------------------\n\
-	PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 1200 MHz  \n\
-	\t	CPU: 600  MHz  \n\
-	\t	PLB: 200  MHz  \n\
-	\t	OPB: 100  MHz  \n\
-	\t	DDR: 200  MHz  \n\
-	----------------------------------------------\n\
-	PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 1333 MHz  \n\
-	\t	CPU: 666  MHz  \n\
-	\t	PLB: 166  MHz  \n\
-	\t	OPB: 83   MHz  \n\
-	\t	DDR: 166  MHz  \n\
-	-----------------------------------------------\n\
-	RCONF: Read current eeprom configuration.      \n\
-	-----------------------------------------------\n\
-	WTEST: Test EEPROM write with predefined values\n\
-	-----------------------------------------------"
-);
-
-#endif	/* CONFIG_CMD_EEPROM */
diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S
deleted file mode 100644
index e15c62249e..0000000000
--- a/board/amcc/makalu/init.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- *   Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Originally based on code provided from Senao and AMCC
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-	.globl  ext_bus_cntlr_init
-ext_bus_cntlr_init:
-	blr
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
deleted file mode 100644
index 2194942cd5..0000000000
--- a/board/amcc/makalu/makalu.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <libfdt.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <linux/errno.h>
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#include <asm/4xx_pcie.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*
- * Board early initialization function
- */
-int board_early_init_f (void)
-{
-	u32 val;
-
-	/*--------------------------------------------------------------------+
-	 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
-	 +--------------------------------------------------------------------+
-	+---------------------------------------------------------------------+
-	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
-	+---------+-----------------------------------+-------+-------+-------+
-	| IRQ 00  | UART0                             | High  | Level | Non   |
-	| IRQ 01  | UART1                             | High  | Level | Non   |
-	| IRQ 02  | IIC0                              | High  | Level | Non   |
-	| IRQ 03  | TBD                               | High  | Level | Non   |
-	| IRQ 04  | TBD                               | High  | Level | Non   |
-	| IRQ 05  | EBM                               | High  | Level | Non   |
-	| IRQ 06  | BGI                               | High  | Level | Non   |
-	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
-	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
-	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
-	| IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
-	| IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
-	| IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
-	| IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
-	| IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
-	| IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
-	| IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
-	| IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
-	| IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
-	| IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
-	| IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
-	| IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
-	| IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
-	| IRQ 23  | Security EIP-94                   | High  | Level | Non   |
-	| IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
-	| IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
-	| IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
-	| IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
-	| IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
-	| IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
-	| IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
-	| IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
-	|----------------------------------------------------------------------
-	| IRQ 32  | MAL Serr                          | High  | Level | Non   |
-	| IRQ 33  | MAL Txde                          | High  | Level | Non   |
-	| IRQ 34  | MAL Rxde                          | High  | Level | Non   |
-	| IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
-	| IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
-	| IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
-	| IRQ 38  | NDFC                              | High  | Level | Non   |
-	| IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
-	| IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
-	| IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
-	| IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
-	| IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
-	| IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
-	| IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
-	| IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
-	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
-	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
-	| IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
-	| IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
-	| IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
-	| IRQ 55  | Serial ROM                        | High  | Level | Non   |
-	| IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
-	| IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
-	| IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
-	|----------------------------------------------------------------------
-	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
-	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
-	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
-	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
-	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
-	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
-	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
-	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
-	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
-	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
-	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
-	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
-	|---------------------------------------------------------------------
-	+---------+-----------------------------------+-------+-------+------*/
-	/*--------------------------------------------------------------------+
-	 | Initialise UIC registers.  Clear all interrupts.  Disable all
-	 | interrupts.
-	 | Set critical interrupt values.  Set interrupt polarities.  Set
-	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
-	 | interrupts again.
-	 +-------------------------------------------------------------------*/
-
-	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC2PR, 0xf7ffffff);	/* Set Interrupt Polarities */
-	mtdcr (UIC2TR, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC1PR, 0xfffac785);	/* Set Interrupt Polarities */
-	mtdcr (UIC1TR, 0x001d0040);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC0ER, 0x0000000a);	/* Disable all interrupts */
-					/* Except cascade UIC0 and UIC1 */
-	mtdcr (UIC0CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC0PR, 0xffbfefef);	/* Set Interrupt Polarities */
-	mtdcr (UIC0TR, 0x00007000);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
-
-	/*
-	 * Note: Some cores are still in reset when the chip starts, so
-	 * take them out of reset
-	 */
-	mtsdr(SDR0_SRST, 0);
-
-	/* Reset PCIe slots */
-	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
-	udelay(100);
-	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * -> Enable USB
-	 */
-	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
-	mtsdr(SDR0_PFC1, val);
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	/* Monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      -CONFIG_SYS_MONITOR_LEN,
-		      0xffffffff,
-		      &flash_info[0]);
-#endif
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}