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authorMarek Vasut <marex@denx.de>2015-12-05 17:55:19 +0100
committerMarek Vasut <marex@denx.de>2015-12-20 03:36:49 +0100
commitb5aaa03634a171d04824336b42790f3e77203bf2 (patch)
tree18d360604bbe6ef3e935f2b99dd8836c5ca98b02 /board/altera
parent6b9cdb716f64d284046221e05bd10673c287bd05 (diff)
downloadu-boot-b5aaa03634a171d04824336b42790f3e77203bf2.tar.gz
arm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'board/altera')
-rw-r--r--board/altera/cyclone5-socdk/socfpga.c40
1 files changed, 0 insertions, 40 deletions
diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c
index 0fbbc3456c..ccb1b4b063 100644
--- a/board/altera/cyclone5-socdk/socfpga.c
+++ b/board/altera/cyclone5-socdk/socfpga.c
@@ -12,10 +12,6 @@
#include <usb/dwc2_udc.h>
#include <usb_mass_storage.h>
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
@@ -31,42 +27,6 @@ int board_init(void)
return 0;
}
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_USB_GADGET
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,