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authorRobert P. J. Day <rpjday@crashcourse.ca>2016-05-15 12:12:07 -0400
committerTom Rini <trini@konsulko.com>2016-05-27 15:39:55 -0400
commit367d789d87cd562cfe4f28c865dd6d342f595baf (patch)
tree1b9a5182aa4f570d89a61130fe44dadd6ca86a8b /board/Marvell
parent2507854e46654042839bf0dcf0d9a291f60c31cf (diff)
downloadu-boot-367d789d87cd562cfe4f28c865dd6d342f595baf.tar.gz
MARVELL: Delete now-superfluous board/Marvell/{common, include} dirs.
With dropping support for some boards and the deletion of some source files, it appears that both of these directories are now superfluous. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Diffstat (limited to 'board/Marvell')
-rw-r--r--board/Marvell/common/bootseq.txt94
-rw-r--r--board/Marvell/common/i2c.h16
-rw-r--r--board/Marvell/common/intel_flash.h170
-rw-r--r--board/Marvell/common/memory.c1374
-rw-r--r--board/Marvell/common/ns16550.c66
-rw-r--r--board/Marvell/common/ns16550.h102
-rw-r--r--board/Marvell/common/serial.c162
-rw-r--r--board/Marvell/include/memory.h173
-rw-r--r--board/Marvell/include/pci.h293
9 files changed, 0 insertions, 2450 deletions
diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
deleted file mode 100644
index 6cae9ea074..0000000000
--- a/board/Marvell/common/bootseq.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-(cpu/mpc7xxx/start.S)
-
-start:
- b boot_cold
-
-start_warm:
- b boot_warm
-
-
-boot_cold:
-boot_warm:
- clear bats
- init l2 (if enabled)
- init altivec (if enabled)
- invalidate l2 (if enabled)
- setup bats (from defines in config_EVB)
- enable_addr_trans: (if MMU enabled)
- enable MSR_IR and MSR_DR
- jump to in_flash
-
-in_flash:
- enable l1 dcache
- gal_low_init: (board/evb64260/sdram_init.S)
- config SDRAM (CFG, TIMING, DECODE)
- init scratch regs (810 + 814)
-
- detect DIMM0 (bank 0 only)
- config SDRAM_PARA0 to 256/512Mbit
- bl sdram_op_mode
- detect bank0 width
- write scratch reg 810
- config SDRAM_PARA0 with results
- config SDRAM_PARA1 with results
-
- detect DIMM1 (bank 2 only)
- config SDRAM_PARA2 to 256/512Mbit
- detect bank2 width
- write scratch reg 814
- config SDRAM_PARA2 with results
- config SDRAM_PARA3 with results
-
- setup device bus timings/width
- setup boot device timings/width
-
- setup CPU_CONF (0x0)
- setup cpu master control register 0x160
- setup PCI0 TIMEOUT
- setup PCI1 TIMEOUT
- setup PCI0 BAR
- setup PCI1 BAR
-
- setup MPP control 0-3
- setup GPP level control
- setup Serial ports multiplex
-
- setup stack pointer (r1)
- setup GOT
- call cpu_init_f
- debug leds
- board_init_f: (common/board.c)
- board_early_init_f:
- remap gt regs?
- map PCI mem/io
- map device space
- clear out interrupts
- init_timebase
- env_init
- serial_init
- console_init_f
- display_options
- initdram: (board/evb64260/evb64260.c)
- detect memory
- for each bank:
- dram_size()
- setup PCI slave memory mappings
- setup SCS
- setup monitor
- alloc board info struct
- init bd struct
- relocate_code: (cpu/mpc7xxx/start.S)
- copy,got,clearbss
- board_init_r(bd, dest_addr) (common/board.c)
- setup bd function pointers
- trap_init
- flash_init: (board/evb64260/flash.c)
- setup bd flash info
- cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
- nothing
- mem_malloc_init
- malloc_bin_reloc
- spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
- env_relocated
- misc_init_r(bd): (board/evb64260/evb64260.c)
- mpsc_init2
diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h
deleted file mode 100644
index a879ea93c8..0000000000
--- a/board/Marvell/common/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- */
-
-#ifndef __I2C_H__
-#define __I2C_H__
-
-/* function declarations */
-uchar i2c_read(uchar, unsigned int, int, uchar*, int);
-
-#endif
diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h
deleted file mode 100644
index 5531f95ca2..0000000000
--- a/board/Marvell/common/intel_flash.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/*
- * acceptable chips types are:
- *
- * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
- */
-
-/* register addresses, valid only following an CHIP_CMD_RD_ID command */
-#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
-#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
-#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
-#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
-
-/* Commands */
-#define CHIP_CMD_RST 0xFF /* reset flash */
-#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
-#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
-#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
-#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
-#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
-#define CHIP_CMD_PROG 0x40 /* program word command */
-#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
-#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
-#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
-#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
-#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
-#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
-#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
-#define CHIP_STAT_VPPS 0x08 /* VPP Status */
-#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
-#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
-#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
-#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
-
-#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
- CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
-#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID
-
-/* dimensions */
-#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
-#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
-#define CHIP_NBLOCKS 128
-#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
-#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * The hymod board has 2 x 28F320J5 chips running in
- * 16 bit mode, for a 32 bit wide bank.
- */
-
-typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
-typedef volatile bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
-
-#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
-#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
-
-#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
-#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
-#define BANK_NBLOCKS CHIP_NBLOCKS
-#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
-#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
-
-#define MAX_BANKS 1 /* only one bank possible */
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_WIDTH - 1)))
-#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
- (bank_size_t)(s) + (BANK_WIDTH - 1)))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_BLKSZ - 1)))
-#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
- (bank_size_t)(s) + (BANK_BLKSZ - 1)))
-
-/* align bank addresses and sizes to bank boundaries */
-#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_SIZE - 1)))
-#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
- (bank_size_t)(s) + (BANK_SIZE - 1)))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
- (bank_size_t)(o))
-
-/* get base address of bank b, given flash base address a */
-#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- (bank_size_t)(b) * BANK_SIZE)
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
- BANK_WIDTH)
-#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
- BANK_BLKSZ)
-#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- BANK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- ((bank_size_t)(r) << BANK_WSHIFT))
-
-/* make a bank address for each chip register address */
-
-#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
-#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
-#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
-#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the bank_word_t type, and take into account the
- * chip width and bank layout
- */
-
-#define BANK_FILL_WORD(o) ((bank_word_t)(o))
-
-/* make a bank word value for each chip cmd/stat/rd value */
-
-/* Commands */
-#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
-#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
-#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
-#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
-#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
-#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
-#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
-#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
-#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
-#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
-#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
-#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
-
-#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
-#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
-#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c
deleted file mode 100644
index 610b411faa..0000000000
--- a/board/Marvell/common/memory.c
+++ /dev/null
@@ -1,1374 +0,0 @@
-/*
- * Copyright - Galileo technology.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- *
- * written or collected and sometimes rewritten by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- */
-
-
-#include <common.h>
-#include "../include/core.h"
-#include "../include/memory.h"
-
-/*******************************************************************************
-* memoryGetBankBaseAddress - Returns the base address of a memory bank.
-* DESCRIPTION:
-* This function returns the base address of one of the SDRAM's memory
-* banks. There are 4 memory banks and each one represents one DIMM side.
-* INPUT:
-* MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit Memory bank base address.
-*******************************************************************************/
-static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
-{
- switch (bank) {
- case BANK0:
- return SCS_0_LOW_DECODE_ADDRESS;
- case BANK1:
- return SCS_1_LOW_DECODE_ADDRESS;
- case BANK2:
- return SCS_2_LOW_DECODE_ADDRESS;
- case BANK3:
- return SCS_3_LOW_DECODE_ADDRESS;
-
- }
- return SCS_0_LOW_DECODE_ADDRESS; /* default value */
-}
-
-unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
-{
- unsigned int base;
- unsigned int regOffset = memoryGetBankRegOffset (bank);
-
- GT_REG_READ (regOffset, &base);
- base = base << 16; /* MV6436x */
- return base;
-}
-
-/*******************************************************************************
-* memoryGetDeviceBaseAddress - Returns the base address of a device.
-* DESCRIPTION:
-* This function returns the base address of a device on the system. There
-* are 5 possible devices (0 - 4 and one boot device) as defined in
-* gtMemory.h. Each of the device parameters is maped to one of the CS
-* (Devices chip selects) base address register.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit Device base address.
-*
-*******************************************************************************/
-static unsigned int memoryGetDeviceRegOffset (DEVICE device)
-{
- switch (device) {
- case DEVICE0:
- return CS_0_LOW_DECODE_ADDRESS;
- case DEVICE1:
- return CS_1_LOW_DECODE_ADDRESS;
- case DEVICE2:
- return CS_2_LOW_DECODE_ADDRESS;
- case DEVICE3:
- return CS_3_LOW_DECODE_ADDRESS;
- case BOOT_DEVICE:
- return BOOTCS_LOW_DECODE_ADDRESS;
- }
- return CS_0_LOW_DECODE_ADDRESS; /* default value */
-}
-
-unsigned int memoryGetDeviceBaseAddress (DEVICE device)
-{
- unsigned int regBase;
- unsigned int regOffset = memoryGetDeviceRegOffset (device);
-
- GT_REG_READ (regOffset, &regBase);
-
- regBase = regBase << 16; /* MV6436x */
- return regBase;
-}
-
-/*******************************************************************************
-* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
-* DESCRIPTION:
-* This function returns the base address of a PCI window. There are 5
-* possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
-* interface as defined in gtMemory.h, used by the CPU's address decoding
-* mechanism.
-* New in MV6436x
-* INPUT:
-* pciWindow - Selects one of the PCI windows as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit PCI window base address.
-*******************************************************************************/
-unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
-{
- unsigned int baseAddrReg, base;
-
- switch (pciWindow) {
- case PCI_0_IO:
- baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
- break;
- case PCI_0_MEM0:
- baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
- break;
- case PCI_0_MEM1:
- baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
- break;
- case PCI_0_MEM2:
- baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
- break;
- case PCI_0_MEM3:
- baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
- break;
- case PCI_1_MEM0:
- baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
- break;
- case PCI_1_MEM1:
- baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
- break;
- case PCI_1_MEM2:
- baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
- break;
- case PCI_1_MEM3:
- baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return 0xffffffff;
- }
- GT_REG_READ (baseAddrReg, &base);
- return (base << 16);
-}
-
-/*******************************************************************************
-* memoryGetBankSize - Returns the size of a memory bank.
-* DESCRIPTION:
-* This function returns the size of memory bank as described in
-* 'gtMemoryGetBankBaseAddress' function.
-* INPUT:
-* bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size memory bank size or 0 for a closed or non populated bank.
-*
-*******************************************************************************/
-unsigned int memoryGetBankSize (MEMORY_BANK bank)
-{
- unsigned int sizeReg, size;
- MEMORY_WINDOW window;
-
- switch (bank) {
- case BANK0:
- sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /* CS_0_SIZE; */
- window = CS_0_WINDOW;
- break;
- case BANK1:
- sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /* CS_1_SIZE; */
- window = CS_1_WINDOW;
- break;
- case BANK2:
- sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /* CS_2_SIZE; */
- window = CS_2_WINDOW;
- break;
- case BANK3:
- sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /* CS_3_SIZE; */
- window = CS_3_WINDOW;
- break;
- default:
- return 0;
- break;
- }
- /* If the window is closed, a size of 0 is returned */
- if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceSize - Returns the size of a device memory space.
-* DESCRIPTION:
-* This function returns the memory space size of a given device.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size of a device memory space.
-*******************************************************************************/
-unsigned int memoryGetDeviceSize (DEVICE device)
-{
- unsigned int sizeReg, size;
- MEMORY_WINDOW window;
-
- switch (device) {
- case DEVICE0:
- sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
- window = DEVCS_0_WINDOW;
- break;
- case DEVICE1:
- sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
- window = DEVCS_1_WINDOW;
- break;
- case DEVICE2:
- sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
- window = DEVCS_2_WINDOW;
- break;
- case DEVICE3:
- sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
- window = DEVCS_3_WINDOW;
- break;
- case BOOT_DEVICE:
- sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
- window = BOOT_CS_WINDOW;
- break;
- default:
- return 0;
- break;
- }
- /* If the window is closed, a size of 0 is returned */
- if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
-* DESCRIPTION:
-* This function returns the size of a PCI window.
-* INPUT:
-* pciWindow - Selects one of the PCI memory windows as defined in
-* Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit size of a PCI memory window.
-*******************************************************************************/
-unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
-{
- unsigned int sizeReg, size;
-
- switch (pciWindow) {
- case PCI_0_IO:
- sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
- break;
- case PCI_0_MEM0:
- sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
- break;
- case PCI_0_MEM1:
- sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
- break;
- case PCI_0_MEM2:
- sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
- break;
- case PCI_0_MEM3:
- sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
- break;
- case PCI_1_MEM0:
- sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
- break;
- case PCI_1_MEM1:
- sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
- break;
- case PCI_1_MEM2:
- sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
- break;
- case PCI_1_MEM3:
- sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return 0x0;
- }
- /* If the memory window is disabled, retrun size = 0 */
- if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
- == MEM_WINDOW_DISABLED)
- return 0;
- GT_REG_READ (sizeReg, &size);
- size = ((size << 16) | 0xffff) + 1;
- return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceWidth - Returns the width of a given device.
-* DESCRIPTION:
-* The MV's device interface supports up to 32 Bit wide devices. A device
-* can have a 1, 2, 4 or 8 Bytes data width. This function returns the
-* width of a device as defined by the user or the operating system.
-* INPUT:
-* device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-* None.
-* RETURN:
-* Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
-*******************************************************************************/
-unsigned int memoryGetDeviceWidth (DEVICE device)
-{
- unsigned int width;
- unsigned int regValue;
-
- GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, &regValue);
- width = (regValue & (BIT20 | BIT21)) >> 20;
- return (BIT0 << width);
-}
-
-/*******************************************************************************
-* memoryMapBank - Set new base address and size for one of the memory
-* banks.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the memory banks
-* (CS0 - CS3). It is the programmer`s responsibility to make sure that
-* there are no conflicts with other memory spaces. When two memory spaces
-* overlap, the MV's behavior is not defined .If a bank needs to be closed,
-* set the 'bankLength' parameter size to 0x0.
-*
-* INPUT:
-* bank - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
-* bankBase - The memory bank base address.
-* bankLength - The memory bank size. This function will decrement the
-* 'bankLength' parameter by one and then check if the size is
-* valid. A valid size must be programed from LSB to MSB as
-* sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-* OUTPUT:
-* None.
-* RETURN:
-* false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
- unsigned int bankLength)
-{
- unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/* PCI_INTERNAL_BAR pciBAR; */
-
- switch (bank) {
- case BANK0:
- baseReg = SCS_0_LOW_DECODE_ADDRESS; /*CS_0_BASE_ADDR; */
- sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /*CS_0_SIZE; */
-/* pciBAR = PCI_CS0_BAR; */
- break;
- case BANK1:
- baseReg = SCS_1_LOW_DECODE_ADDRESS; /*CS_1_BASE_ADDR; */
- sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /*CS_1_SIZE; */
- /* pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
- break;
- case BANK2:
- baseReg = SCS_2_LOW_DECODE_ADDRESS; /*CS_2_BASE_ADDR; */
- sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /*CS_2_SIZE; */
-/* pciBAR = PCI_CS2_BAR;*/
- break;
- case BANK3:
- baseReg = SCS_3_LOW_DECODE_ADDRESS; /*CS_3_BASE_ADDR; */
- sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /*CS_3_SIZE; */
-/* pciBAR = PCI_CS3_BAR; */
- break;
- default:
- return false;
- }
- /* If the size is 0, the window will be disabled */
- if (bankLength == 0) {
- MemoryDisableWindow (CS_0_WINDOW << bank);
- /* Disable the BAR from the PCI slave side */
-/* gtPci0DisableInternalBAR(pciBAR); */
-/* gtPci1DisableInternalBAR(pciBAR); */
- return true;
- }
- /* The base address must be aligned to the size */
- if ((bankBase % bankLength) != 0) {
- return false;
- }
- if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
- newBase = bankBase >> 16;
- newSize = bankLength >> 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = newSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
-#ifdef DEBUG
- {
- unsigned int oldBase, oldSize;
-
- GT_REG_READ (baseReg, &oldBase);
- GT_REG_READ (sizeReg + 8, &oldSize);
-
- printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
- bank, oldBase, oldSize, newBase, newSize);
- }
-#endif
- /* writing the new values */
- GT_REG_WRITE (baseReg, newBase);
- GT_REG_WRITE (sizeReg, newSize - 1);
- /* Enable back the window */
- MemoryEnableWindow (CS_0_WINDOW << bank);
- /* Enable the BAR from the PCI slave side */
-/* gtPci0EnableInternalBAR(pciBAR); */
-/* gtPci1EnableInternalBAR(pciBAR); */
- return true;
- }
- return false;
-}
-
-
-/*******************************************************************************
-* memoryMapDeviceSpace - Set new base address and size for one of the device
-* windows.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the device windows
-* (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
-* that there are no conflicts with other memory spaces. When two memory
-* spaces overlap, the MV's behavior is not defined .If a device window
-* needs to be closed, set the 'deviceLength' parameter size to 0x0.
-*
-* INPUT:
-* device - One of the device windows (DEV_CS0-DEV_CS3) as
-* defined in gtMemory.h.
-* deviceBase - The device window base address.
-* deviceLength - The device window size. This function will decrement
-* the 'deviceLength' parameter by one and then
-* check if the size is valid. A valid size must be
-* programed from LSB to MSB as sequence of '1's
-* followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
- unsigned int deviceLength)
-{
- unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/* PCI_INTERNAL_BAR pciBAR;*/
-
- switch (device) {
- case DEVICE0:
- baseReg = CS_0_LOW_DECODE_ADDRESS; /*DEV_CS0_BASE_ADDR; */
- sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
-/* pciBAR = PCI_DEV_CS0_BAR; */
- break;
- case DEVICE1:
- baseReg = CS_1_LOW_DECODE_ADDRESS; /*DEV_CS1_BASE_ADDR; */
- sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
-/* pciBAR = PCI_DEV_CS1_BAR; */
- break;
- case DEVICE2:
- baseReg = CS_2_LOW_DECODE_ADDRESS; /*DEV_CS2_BASE_ADDR; */
- sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
-/* pciBAR = PCI_DEV_CS2_BAR; */
- break;
- case DEVICE3:
- baseReg = CS_3_LOW_DECODE_ADDRESS; /*DEV_CS3_BASE_ADDR; */
- sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
-/* pciBAR = PCI_DEV_CS3_BAR; */
- break;
- case BOOT_DEVICE:
- baseReg = BOOTCS_LOW_DECODE_ADDRESS; /*BOOTCS_BASE_ADDR; */
- sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
-/* pciBAR = PCI_BOOT_CS_BAR; */
- break;
- default:
- return false;
- }
- if (deviceLength == 0) {
- MemoryDisableWindow (DEVCS_0_WINDOW << device);
- /* Disable the BAR from the PCI slave side */
-/* gtPci0DisableInternalBAR(pciBAR); */
-/* gtPci1DisableInternalBAR(pciBAR); */
- return true;
- }
- /* The base address must be aligned to the size */
- if ((deviceBase % deviceLength) != 0) {
- return false;
- }
- if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
- newBase = deviceBase >> 16;
- newSize = deviceLength >> 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = newSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- /* writing the new values */
- GT_REG_WRITE (baseReg, newBase);
- GT_REG_WRITE (sizeReg, newSize - 1);
- MemoryEnableWindow (DEVCS_0_WINDOW << device);
- /* Enable the BAR from the PCI slave side */
-/* gtPci0EnableInternalBAR(pciBAR); */
-/* gtPci1EnableInternalBAR(pciBAR); */
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* MemorySetPciWindow - Set new base address and size for one of the PCI
-* windows.
-*
-* DESCRIPTION:
-* The CPU interface address decoding map consists of 21 address windows
-* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-* space. Each address window is defined by two registers - base and size.
-* The CPU address is compared with the values in the various CPU windows
-* until a match is found and the address is than targeted to that window.
-* This function sets new base and size for one the PCI windows
-* (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
-* that there are no conflicts with other memory spaces. When two memory
-* spaces overlap, the MV's behavior is not defined. If a PCI window
-* needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
-*
-* INPUT:
-* pciWindow - One of the PCI windows as defined in gtMemory.h.
-* pciWindowBase - The PCI window base address.
-* pciWindowSize - The PCI window size. This function will decrement the
-* 'pciWindowSize' parameter by one and then check if the
-* size is valid. A valid size must be programed from LSB
-* to MSB as sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
- unsigned int pciWindowSize)
-{
- unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
-
- switch (pciWindow) {
- case PCI_0_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
- sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
- break;
- case PCI_0_MEM0:
- baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
- sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
- break;
- case PCI_0_MEM1:
- baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
- sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
- break;
- case PCI_0_MEM2:
- baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
- sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
- break;
- case PCI_0_MEM3:
- baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
- sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
- sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
- break;
- case PCI_1_MEM0:
- baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
- sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
- break;
- case PCI_1_MEM1:
- baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
- sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
- break;
- case PCI_1_MEM2:
- baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
- sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
- break;
- case PCI_1_MEM3:
- baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
- sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- return false;
- }
- if (pciWindowSize == 0) {
- MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
- return true;
- }
- /* The base address must be aligned to the size */
- if ((pciWindowBase % pciWindowSize) != 0) {
- return false;
- }
- if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
- pciWindowBase >>= 16;
- pciWindowSize >>= 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = pciWindowSize - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- GT_REG_WRITE (sizeReg, pciWindowSize - 1);
- GT_REG_READ (baseAddrReg, &currentLow);
- pciWindowBase =
- (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
- GT_REG_WRITE (baseAddrReg, pciWindowBase);
- MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internal
-* registers memory space.
-*
-* DESCRIPTION:
-* This function set new base address for the internal registers memory
-* space (the size is fixed and cannot be modified). The function does not
-* handle overlapping with other memory spaces, it is the programer's
-* responsibility to ensure that overlapping does not occur.
-* When two memory spaces overlap, the MV's behavior is not defined.
-*
-* INPUT:
-* internalRegBase - new base address for the internal registers memory
-* space.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* true on success, false on failure
-*
-*******************************************************************************/
-/********************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internals
-* registers.
-*
-* INPUTS: unsigned int internalRegBase - The new base address.
-* RETURNS: true on success, false on failure
-*********************************************************************/
-bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
-{
- unsigned int currentValue;
- unsigned int internalValue = internalRegBase;
-
- internalRegBase = (internalRegBase >> 16);
- GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
- internalRegBase = (currentValue & 0xff000000) | internalRegBase;
- GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
- /* initializing also the global variable 'internalRegBaseAddr' */
-/* gtInternalRegBaseAddr = internalValue; */
- INTERNAL_REG_BASE_ADDR = internalValue;
- return true;
-}
-
-/*******************************************************************************
-* memoryGetInternalRegistersSpace - Returns the internal registers Base
-* address.
-*
-* DESCRIPTION:
-* This function returns the base address of the internal registers
-* memory space .
-*
-* INPUT:
-* None.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* 32 bit base address of the internal registers memory space.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalRegistersSpace (void)
-{
- unsigned int currentValue = 0;
-
- GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
- return ((currentValue & 0x000fffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
-*
-* DESCRIPTION:
-* The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-* funcnion return the SRAM's base address.
-* INPUT:
-* None.
-* OUTPUT:
-* None.
-* RETURN:
-* 32 bit SRAM's base address.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalSramBaseAddr (void)
-{
- return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
-*
-* DESCRIPTION:
-* The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-* function sets a new base address to the SRAM .
-* INPUT:
-* sramBaseAddress - The SRAM's base address.
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*
-*******************************************************************************/
-void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
-{
- GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
-}
-
-/*******************************************************************************
-* memorySetProtectRegion - Set protection mode for one of the 8 regions.
-*
-* DESCRIPTION:
-* The CPU interface supports configurable access protection. This includes
-* up to eight address ranges defined to a different protection type :
-* whether the address range is cacheable or not, whether it is writable or
-* not , and whether it is accessible or not. A Low and High registers
-* define each window while the minimum address range of each window is
-* 1Mbyte. An address driven by the CPU, in addition to the address
-* decoding and remapping process, is compared against the eight Access
-* Protection Low/High registers , if an address matches one of the windows
-* , the MV device checks the transaction type against the protection bits
-* defined in CPU Access Protection register, to determine if the access is
-* allowed. This function set a protection mode to one of the 8 possible
-* regions.
-* NOTE:
-* The CPU address windows are restricted to a size of 2 power n and the
-* start address must be aligned to the window size. For example, if using
-* a 16 MB window, the start address bits [23:0] must be 0.The MV's
-* internal registers space is not protected, even if the access protection
-* windows contain this space.
-*
-* INPUT:
-* region - selects which region to be configured. The values defined in
-* gtMemory.h:
-*
-* - MEM_REGION0
-* - MEM_REGION1
-* - etc.
-*
-* memAccess - Allows or forbids access (read or write ) to the region. The
-* values defined in gtMemory.h:
-*
-* - MEM_ACCESS_ALLOWED
-* - MEM_ACCESS_FORBIDEN
-*
-* memWrite - CPU write protection to the region. The values defined in
-* gtMemory.h:
-*
-* - MEM_WRITE_ALLOWED
-* - MEM_WRITE_FORBIDEN
-*
-* cacheProtection - Defines whether caching the region is allowed or not.
-* The values defined in gtMemory.h:
-*
-* - MEM_CACHE_ALLOWED
-* - MEM_CACHE_FORBIDEN
-*
-* baseAddress - the region's base Address.
-* regionSize - The region's size. This function will decrement the
-* 'regionSize' parameter by one and then check if the size
-* is valid. A valid size must be programed from LSB to MSB
-* as sequence of '1's followed by sequence of '0's.
-* To close a memory window simply set the size to 0.
-*
-* NOTE!!!
-* The size must be in 64Kbyte granularity.
-* The base address must be aligned to the size.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
- MEMORY_ACCESS memAccess,
- MEMORY_ACCESS_WRITE memWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress, unsigned int size)
-{
- unsigned int dataForReg, temp, rShift;
-
- if (size == 0) {
- GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
- 0x0);
- return true;
- }
- /* The base address must be aligned to the size. */
- if (baseAddress % size != 0) {
- return false;
- }
- if (size >= MINIMUM_ACCESS_WIN_SIZE) {
- baseAddress = ((baseAddress >> 16) & 0xfffff);
- dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
- ((memWrite << 21) & BIT21) | ((cacheProtection << 22)
- & BIT22) | BIT31;
- GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
- dataForReg);
- size >>= 16;
- /* Checking that the size is a sequence of '1' followed by a
- sequence of '0' starting from LSB to MSB. */
- temp = size - 1;
- for (rShift = 0; rShift < 16; rShift++) {
- temp = temp >> rShift;
- if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
- /* or the size is not valid */
- if (temp > 0x0)
- return false;
- else
- break;
- }
- }
- GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
- size - 1);
- return true;
- }
- return false;
-}
-
-/*******************************************************************************
-* gtMemoryDisableProtectRegion - Disable a protected window.
-*
-* DESCRIPTION:
-* This function disable a protected window set by
-* 'gtMemorySetProtectRegion' function.
-*
-* INPUT:
-* window - one of the 4 windows ( defined in gtMemory.h ).
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
-{
- RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
- BIT31);
-}
-
-/*******************************************************************************
-* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
-*
-* DESCRIPTION:
-* In addition to the address decoding mechanism, the CPU has an address
-* remapping mechanism to be used by every PCI decoding window. Each PCI
-* window can be remaped to a desired address target according to the remap
-* value within the remap register. The address remapping is useful when a
-* CPU address range must be reallocated to a different location on the
-* PCI bus. Also, it enables CPU access to a PCI agent located above the
-* 4Gbyte space. On system boot, each of the PCI memory spaces is maped to
-* a defualt value (see CPU interface section in the MV spec for the
-* default values). The remap mechanism does not always produce the desired
-* address on the PCI bus because of the remap mechanism way of working
-* (to fully understand why, please see the 'Address Remapping' section in
-* the MV's spec). Therefor, this function sets a desired remap value to
-* one of the PCI memory windows and return the effective address that
-* should be used when exiting the PCI memory window. You should ALWAYS use
-* the returned value by this function when remapping a PCI window and
-* exiting it. If for example the base address of PCI0 memory 0 is
-* 0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
-* the function will return the value of 0x91000000 that MUST
-* be used to exit this memory window in order to achive the deisred
-* remapping.
-*
-* INPUT:
-* memoryWindow - One of the PCI memory windows as defined in Memory.h
-* remapValueLow - The low remap value.
-* remapValueHigh - The high remap value.
-* OUTPUT:
-* None.
-*
-* RETURN:
-* The effective base address to exit the PCI, or 0xffffffff if one of the
-* parameters is erroneous or the effective base address is higher the top
-* decode value.
-*
-*******************************************************************************/
-unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
- unsigned int remapValueHigh,
- unsigned int remapValueLow)
-{
- unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
- unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
- unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
-
- /* Initializing the base and size variables of the PCI
- memory windows */
- switch (memoryWindow) {
- case PCI_0_IO:
- pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_IO_SIZE;
- remapRegLow = PCI_0_IO_ADDR_REMAP;
- remapRegHigh = PCI_0_IO_ADDR_REMAP;
- break;
- case PCI_0_MEM0:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
- remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM1:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
- remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM2:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
- remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
- break;
- case PCI_0_MEM3:
- pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
- pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
- remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
- remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
- break;
-#ifdef INCLUDE_PCI_1
- case PCI_1_IO:
- pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_IO_SIZE;
- remapRegLow = PCI_1_IO_ADDR_REMAP;
- remapRegHigh = PCI_1_IO_ADDR_REMAP;
- break;
- case PCI_1_MEM0:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
- remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM1:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
- remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM2:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
- remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
- break;
- case PCI_1_MEM3:
- pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
- pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
- remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
- remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
- break;
-#endif /* INCLUDE_PCI_1 */
- default:
- /* Retrun an invalid effective base address */
- return 0xffffffff;
- }
- /* Writing the remap value to the remap regisers */
- GT_REG_WRITE (remapRegHigh, remapValueHigh);
- GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
- /* Reading the values from the base address and size registers */
- baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
- windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
- /* Start calculating the effective Base Address */
- effectiveBaseAddress = baseAddrValue << 16;
- /* The effective base address will be combined from the chopped (if any)
- remap value (according to the size value and remap mechanism) and the
- window's base address */
- effectiveBaseAddress |=
- (((windowSizeValue << 16) | 0xffff) & remapValueLow);
- /* If the effectiveBaseAddress exceed the window boundaries return an
- invalid value. */
- if (effectiveBaseAddress >
- ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
- return 0xffffffff;
- return effectiveBaseAddress;
-}
-
-/********************************************************************
-* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency.
-*
-*
-* Inputs: SNOOP_REGION region - One of the four regions.
-* SNOOP_TYPE snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* unsigned int baseAddress - Base Address of this region.
-* unsigned int topAddress - Top Address of this region.
-* Returns: false if one of the parameters is wrong and true else
-*********************************************************************/
-/* evb6260 code */
-#if 0
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
- MEMORY_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
- return false;
- snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
- snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
- if(regionLength == 0) /* closing the region */
- {
- GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
- GT_REG_WRITE(snoopXtopAddress,0);
- return true;
- }
- baseAddress = baseAddress & 0xffff0000;
- data = (baseAddress >> 16) | snoopType << 16;
- GT_REG_WRITE(snoopXbaseAddress,data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
- return true;
-}
-#endif
-
-/********************************************************************
-* memoryRemapAddress - This fubction used for address remapping.
-*
-*
-* Inputs: regOffset: remap register
-* remapValue :
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*
-* Not needed function To_do !!!!
-*********************************************************************/
-bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
-{
- unsigned int valueForReg;
-
- valueForReg = (remapValue & 0xfff00000) >> 20;
- GT_REG_WRITE (remapReg, valueForReg);
- return true;
-}
-
-/*******************************************************************************
-* memoryGetDeviceParam - Extract the device parameters from the device bank
-* parameters register.
-*
-* DESCRIPTION:
-* To allow interfacing with very slow devices and fast synchronous SRAMs,
-* each device can be programed to different timing parameters. Each bank
-* has its own parameters register. Bank width can be programmed to 8, 16,
-* or 32-bits. Bank timing parameters can be programmed to support
-* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-* Controllers). The MV allows you to set timing parameters and width for
-* each device through parameters register .
-* This function extracts the parameters described from the Device Bank
-* parameters register and fills the given 'deviceParam' (defined in
-* gtMemory.h) structure with the read data.
-*
-* INPUT:
-* deviceParam - pointer to a structure DEVICE_PARAM (defined in
-* Memory.h).For details about each structure field please
-* see the device timing parameter section in the MV
-* datasheet.
-* deviceNum - Select on of the five device banks (defined in
-* Memory.h) :
-*
-* - DEVICE0
-* - DEVICE1
-* - DEVICE2
-* - etc.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memoryGetDeviceParam - This function used for getting device parameters from
-* DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK
-* PARAMETERS REGISTER
-* - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-
-bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
- unsigned int valueOfReg;
- unsigned int calcData;
-
- if (deviceNum > 4)
- return false;
- GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
- calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
- deviceParam->turnOff = calcData; /* Turn Off */
-
- calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
- deviceParam->acc2First = calcData; /* Access To First */
-
- calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
- deviceParam->acc2Next = calcData; /* Access To Next */
-
- calcData =
- ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
- deviceParam->ale2Wr = calcData; /* Ale To Write */
-
- calcData = ((0x1c000 & valueOfReg) >> 14) +
- ((BIT26 & valueOfReg) >> 23);
- deviceParam->wrLow = calcData; /* Write Active */
-
- calcData = ((0xe0000 & valueOfReg) >> 17) +
- ((BIT27 & valueOfReg) >> 24);
- deviceParam->wrHigh = calcData; /* Write High */
-
- calcData = ((0x300000 & valueOfReg) >> 20);
- deviceParam->deviceWidth = (BIT0 << calcData); /* In bytes */
- calcData = ((0x30000000 & valueOfReg) >> 28);
- deviceParam->badrSkew = calcData; /* Cycles gap between BAdr
- toggle to read data sample. */
- calcData = ((0x40000000 & valueOfReg) >> 30);
- deviceParam->DPEn = calcData; /* Data Parity enable */
- return true;
-}
-
-/*******************************************************************************
-* memorySetDeviceParam - Set new parameters for a device.
-*
-*
-* DESCRIPTION:
-* To allow interfacing with very slow devices and fast synchronous SRAMs,
-* each device can be programed to different timing parameters. Each bank
-* has its own parameters register. Bank width can be programmed to 8, 16,
-* or 32-bits. Bank timing parameters can be programmed to support
-* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-* Controllers). The MV allows you to set timing parameters and width for
-* each device through parameters register. This function set new
-* parameters to a device Bank from the delivered structure 'deviceParam'
-* (defined in gtMemory.h). The structure must be initialized with data
-* prior to the use of these function.
-*
-* INPUT:
-* deviceParam - pointer to a structure DEVICE_PARAM (defined in
-* Memory.h).For details about each structure field please
-* see the device timing parameter section in the MV
-* datasheet.
-* deviceNum - Select on of the five device banks (defined in
-* Memory.h) :
-*
-* - DEVICE0
-* - DEVICE1
-* - DEVICE2
-* - etc.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memorySetDeviceParam - This function used for setting device parameters to
-* DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK
-* PARAMETERS REGISTER
-* - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
- unsigned int valueForReg;
-
- if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
- (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
- (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
- (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
- return false;
- }
- valueForReg = (((deviceParam->turnOff) & 0x7) |
- (((deviceParam->turnOff) & 0x8) << 19) |
- (((deviceParam->acc2First) & 0xf) << 3) |
- (((deviceParam->acc2First) & 0x10) << 19) |
- (((deviceParam->acc2Next) & 0xf) << 7) |
- (((deviceParam->acc2Next) & 0x10) << 20) |
- (((deviceParam->ale2Wr) & 0x7) << 11) |
- (((deviceParam->ale2Wr) & 0xf) << 22) |
- (((deviceParam->wrLow) & 0x7) << 14) |
- (((deviceParam->wrLow) & 0xf) << 23) |
- (((deviceParam->wrHigh) & 0x7) << 17) |
- (((deviceParam->wrHigh) & 0xf) << 24) |
- (((deviceParam->badrSkew) & 0x3) << 28) |
- (((deviceParam->DPEn) & 0x1) << 30));
-
- /* insert the device width: */
- switch (deviceParam->deviceWidth) {
- case 1:
- valueForReg = valueForReg | _8BIT;
- break;
- case 2:
- valueForReg = valueForReg | _16BIT;
- break;
- case 4:
- valueForReg = valueForReg | _32BIT;
- break;
- default:
- valueForReg = valueForReg | _8BIT;
- break;
- }
- GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
- return true;
-}
-
-/*******************************************************************************
-* MemoryDisableWindow - Disable a memory space by the disable bit.
-* DESCRIPTION:
-* This function disables one of the 21 availiable windows dedicated for
-* the CPU decoding mechanism. Its possible to combine several windows with
-* the OR command.
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*******************************************************************************/
-void MemoryDisableWindow (MEMORY_WINDOW window)
-{
- SET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryEnableWindow - Enable a memory space that was disabled by
-* 'MemoryDisableWindow'.
-* DESCRIPTION:
-* This function enables one of the 21 availiable windows dedicated for the
-* CPU decoding mechanism. Its possible to combine several windows with the
-* OR command.
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* None.
-*******************************************************************************/
-void MemoryEnableWindow (MEMORY_WINDOW window)
-{
- RESET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryGetMemWindowStatus - This function check whether the memory window is
-* disabled or not.
-* DESCRIPTION:
-* This function checks if the given memory window is closed .
-* INPUT:
-* window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-* None.
-* RETURN:
-* true for a closed window, false otherwise .
-*******************************************************************************/
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
-{
- if (GTREGREAD (BASE_ADDR_ENABLE) & window)
- return MEM_WINDOW_DISABLED;
- return MEM_WINDOW_ENABLED;
-}
diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c
deleted file mode 100644
index 7839b68d42..0000000000
--- a/board/Marvell/common/ns16550.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/powerpc/boot/ns16550.c)
- * modified to use CONFIG_SYS_ISA_MEM and new defines
- *
- * further modified by Josh Huber <huber@mclx.com> to support
- * the DUART on the Galileo Eval board. (db64360)
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-#ifdef ZUMA_NTL
-/* no 16550 device */
-#else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
- (NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
-};
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
- volatile struct NS16550 *com_port;
-
- com_port = (struct NS16550 *) COM_PORTS[chan];
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
-
- /* Clear & enable FIFOs */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
- return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
-
- /* Clear & enable FIFOs */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
- while ((com_port->lsr & LSR_THRE) == 0);
- com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
- while ((com_port->lsr & LSR_DR) == 0);
- return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
- return ((com_port->lsr & LSR_DR) != 0);
-}
-#endif
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
deleted file mode 100644
index 9306381353..0000000000
--- a/board/Marvell/common/ns16550.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/powerpc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CONFIG_SYS_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
- * further modified to support the DUART in the Galileo eval board
- * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- */
-
-#ifndef __NS16550_H__
-#define __NS16550_H__
-
-/* the padding is necessary because on the galileo board the UART is
- wired in with the 3 address lines shifted over by 2 bits */
-struct NS16550
-{
- unsigned char rbr; /* 0 = 0-3*/
- int pad1:24;
-
- unsigned char ier; /* 1 = 4-7*/
- int pad2:24;
-
- unsigned char fcr; /* 2 = 8-b*/
- int pad3:24;
-
- unsigned char lcr; /* 3 = c-f*/
- int pad4:24;
-
- unsigned char mcr; /* 4 = 10-13*/
- int pad5:24;
-
- unsigned char lsr; /* 5 = 14-17*/
- int pad6:24;
-
- unsigned char msr; /* 6 =18-1b*/
- int pad7:24;
-
- unsigned char scr; /* 7 =1c-1f*/
- int pad8:24;
-} __attribute__ ((packed));
-
-/* aliases */
-#define thr rbr
-#define iir fcr
-#define dll rbr
-#define dlm ier
-
-#define FCR_FIFO_EN 0x01 /*fifo enable*/
-#define FCR_RXSR 0x02 /*receiver soft reset*/
-#define FCR_TXSR 0x04 /*transmitter soft reset*/
-
-
-#define MCR_DTR 0x01
-#define MCR_RTS 0x02
-#define MCR_DMA_EN 0x04
-#define MCR_TX_DFR 0x08
-
-
-#define LCR_WLS_MSK 0x03 /* character length slect mask*/
-#define LCR_WLS_5 0x00 /* 5 bit character length */
-#define LCR_WLS_6 0x01 /* 6 bit character length */
-#define LCR_WLS_7 0x02 /* 7 bit character length */
-#define LCR_WLS_8 0x03 /* 8 bit character length */
-#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN 0x08 /* Parity eneble*/
-#define LCR_EPS 0x10 /* Even Parity Select*/
-#define LCR_STKP 0x20 /* Stick Parity*/
-#define LCR_SBRK 0x40 /* Set Break*/
-#define LCR_BKSE 0x80 /* Bank select enable*/
-
-#define LSR_DR 0x01 /* Data ready */
-#define LSR_OE 0x02 /* Overrun */
-#define LSR_PE 0x04 /* Parity error */
-#define LSR_FE 0x08 /* Framing error */
-#define LSR_BI 0x10 /* Break */
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40 /* Xmitter empty */
-#define LSR_ERR 0x80 /* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1 0x03
-
-
-#define COM1 0x03F8
-#define COM2 0x02F8
-
-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
-
-typedef struct NS16550 *NS16550_t;
-
-extern const NS16550_t COM_PORTS[];
-
-#endif
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
deleted file mode 100644
index 432aa0660e..0000000000
--- a/board/Marvell/common/serial.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * serial.c - serial support for the gal ev board
- */
-
-/* supports both the 16650 duart and the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../include/memory.h"
-
-#include "ns16550.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_MPSC
-static int marvell_serial_init(void)
-{
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
- int clock_divisor = 230400 / gd->baudrate;
-#endif
-
- mpsc_init (gd->baudrate);
-
- /* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
- return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
- if (c == '\n')
- mpsc_putchar ('\r');
-
- mpsc_putchar (c);
-}
-
-static int marvell_serial_getc(void)
-{
- return mpsc_getchar ();
-}
-
-static int marvell_serial_tstc(void)
-{
- return mpsc_test_char ();
-}
-
-static void marvell_serial_setbrg(void)
-{
- galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-#else /* ! CONFIG_MPSC */
-
-static int marvell_serial_init(void)
-{
- int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- (void) NS16550_init (0, clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- (void) NS16550_init (1, clock_divisor);
-#endif
- return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
- if (c == '\n')
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-static int marvell_serial_getc(void)
-{
- return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static int marvell_serial_tstc(void)
-{
- return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static void marvell_serial_setbrg(void)
-{
- int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-#endif /* CONFIG_MPSC */
-
-static struct serial_device marvell_serial_drv = {
- .name = "marvell_serial",
- .start = marvell_serial_init,
- .stop = NULL,
- .setbrg = marvell_serial_setbrg,
- .putc = marvell_serial_putc,
- .puts = default_serial_puts,
- .getc = marvell_serial_getc,
- .tstc = marvell_serial_tstc,
-};
-
-void marvell_serial_initialize(void)
-{
- serial_register(&marvell_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &marvell_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h
deleted file mode 100644
index 0947b6e4ff..0000000000
--- a/board/Marvell/include/memory.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Memory.h - Memory mappings and remapping functions declarations */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCmemoryh
-#define __INCmemoryh
-
-/* includes */
-
-#include "core.h"
-
-/* defines */
-
-#define DONT_MODIFY 0xffffffff
-#define PARITY_SUPPORT 0x40000000
-#define MINIMUM_MEM_BANK_SIZE 0x10000
-#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000
-#define MINIMUM_PCI_WINDOW_SIZE 0x10000
-#define MINIMUM_ACCESS_WIN_SIZE 0x10000
-
-#define _8BIT 0x00000000
-#define _16BIT 0x00100000
-#define _32BIT 0x00200000
-#define _64BIT 0x00300000
-
-/* typedefs */
-
- typedef struct deviceParam
-{ /* boundary values */
- unsigned int turnOff; /* 0x0 - 0xf */
- unsigned int acc2First; /* 0x0 - 0x1f */
- unsigned int acc2Next; /* 0x0 - 0x1f */
- unsigned int ale2Wr; /* 0x0 - 0xf */
- unsigned int wrLow; /* 0x0 - 0xf */
- unsigned int wrHigh; /* 0x0 - 0xf */
- unsigned int badrSkew; /* 0x0 - 0x2 */
- unsigned int DPEn; /* 0x0 - 0x1 */
- unsigned int deviceWidth; /* in Bytes */
-} DEVICE_PARAM;
-
-
-typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
-typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
-
-/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
- MEM_REGION3,MEM_REGION4,MEM_REGION5, \
- MEM_REGION6,MEM_REGION7} \
- MEMORY_PROTECT_REGION;*/
-/* There are four possible windows that can be defined as protected */
-typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
- MEM_WINDOW3
- } MEMORY_PROTECT_WINDOW;
-/* When defining a protected window , this paramter indicates whether it
- is accessible or not */
-typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
- MEMORY_ACCESS;
-typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
- MEMORY_ACCESS_WRITE;
-typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
- MEMORY_CACHE_PROTECT;
-typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
- MEMORY_SNOOP_TYPE;
-typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
- MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
- MEMORY_SNOOP_REGION;
-
-/* There are 21 memory windows dedicated for the varios interfaces (PCI,
- devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
- address decoding mechanism. */
-typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
- CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
- DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
- DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
- BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
- PCI_0_MEM0_WINDOW = BIT10,
- PCI_0_MEM1_WINDOW = BIT11,
- PCI_0_MEM2_WINDOW = BIT12,
- PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
- PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
- PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
- INTEGRATED_SRAM_WINDOW = BIT19,
- INTERNAL_SPACE_WINDOW = BIT20,
- ALL_WINDOWS = 0X1FFFFF
- } MEMORY_WINDOW;
-
-typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
- } MEMORY_WINDOW_STATUS;
-
-
-typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
-#ifdef INCLUDE_PCI_1
- ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
-#endif /* INCLUDE_PCI_1 */
- } PCI_MEM_WINDOW;
-
-
-/* -------------------------------------------------------------------------------------------------*/
-
-/* functions */
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
-unsigned int memoryGetDeviceBaseAddress(DEVICE device);
-/* New at MV6436x */
-unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
-unsigned int memoryGetBankSize(MEMORY_BANK bank);
-unsigned int memoryGetDeviceSize(DEVICE device);
-unsigned int memoryGetDeviceWidth(DEVICE device);
-/* New at MV6436x */
-unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
-
-/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
-/* Set a new base and size for one of the memory banks (CS0 - CS3) */
-bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
- unsigned int bankSize);
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
-
-/* Change the Internal Register Base Address to a new given Address. */
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
-/* returns internal Register Space Base Address. */
-unsigned int memoryGetInternalRegistersSpace(void);
-
-/* Returns the integrated SRAM Base Address. */
-unsigned int memoryGetInternalSramBaseAddr(void);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Set new base address for the integrated SRAM. */
-void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Delete a protection feature to a given space. */
-void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Writes a new remap value to the remap register */
-unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
- unsigned int remapValueHigh,
- unsigned int remapValueLow);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Configurate the protection feature to a given space. */
-bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
- MEMORY_ACCESS gtMemoryAccess,
- MEMORY_ACCESS_WRITE gtMemoryWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress,
- unsigned int size);
-
-/* Configurate the protection feature to a given space. */
-/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
- MEMORY_ACCESS memoryAccess,
- MEMORY_ACCESS_WRITE memoryWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress,
- unsigned int regionLength); */
-/* Configurate the snoop feature to a given space. */
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
- MEMORY_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength);
-
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-/* Set a new base and size for one of the PCI windows. */
-bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
- unsigned int pciWindowSize);
-
-/* Disable or enable one of the 21 windows dedicated for the CPU's
- address decoding mechanism */
-void MemoryDisableWindow(MEMORY_WINDOW window);
-void MemoryEnableWindow (MEMORY_WINDOW window);
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
-#endif /* __INCmemoryh */
diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h
deleted file mode 100644
index 572e0d345d..0000000000
--- a/board/Marvell/include/pci.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/* PCI.h - PCI functions header file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCpcih
-#define __INCpcih
-
-/* includes */
-
-#include "core.h"
-#include "memory.h"
-
-/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
-#define PCI_MAX_DEVICES 22
-
-
-/* Macros */
-
-/* The next Macros configurate the initiator board (SELF) or any any agent on
- the PCI to become: MASTER, response to MEMORY transactions , response to
- IO transactions or TWO both MEMORY_IO transactions. Those configuration
- are for both PCI0 and PCI1. */
-
-#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
- pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
-
-#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
- pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \
- PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
- pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define MASTER_ENABLE BIT2
-#define MEMORY_ENABLE BIT1
-#define I_O_ENABLE BIT0
-#define SELF 32
-
-/* Agent on the PCI bus may have up to 6 BARS. */
-#define BAR0 0x10
-#define BAR1 0x14
-#define BAR2 0x18
-#define BAR3 0x1c
-#define BAR4 0x20
-#define BAR5 0x24
-#define BAR_SEL_MEM_IO BIT0
-#define BAR_MEM_TYPE_32_BIT NO_BIT
-#define BAR_MEM_TYPE_BELOW_1M BIT1
-#define BAR_MEM_TYPE_64_BIT BIT2
-#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2)
-#define BAR_MEM_TYPE_MASK (BIT1 | BIT2)
-#define BAR_PREFETCHABLE BIT3
-#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3)
-
-/* Defines for the access regions. */
-#define PREFETCH_ENABLE BIT12
-#define PREFETCH_DISABLE NO_BIT
-#define DELAYED_READ_ENABLE BIT13
-/* #define CACHING_ENABLE BIT14 */
-/* aggressive prefetch: PCI slave prefetch two burst in advance*/
-#define AGGRESSIVE_PREFETCH BIT16
-/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
-/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
-#define MAX_BURST_4 NO_BIT
-#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
-#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
-#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
-#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
-#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
-#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
-#define PCI_ACCESS_PROTECT BIT28
-#define PCI_WRITE_PROTECT BIT29
-
-/* typedefs */
-
-typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
- REGION6,REGION7} PCI_ACCESS_REGIONS;
-
-typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
-typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
-
-typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
- PCI_SNOOP_TYPE;
-typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
- PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
- PCI_SNOOP_REGION;
-
-typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
-typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
- PCI_REGION2,PCI_REGION3,
- PCI_IO}
- PCI_REGION;
-
-/*ronen 7/Dec/03 */
-typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
- PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
- PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
- PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
- PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
- PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
- PCI_LAST_BAR} PCI_INTERNAL_BAR;
-
-typedef struct pciBar {
- unsigned int detectBase;
- unsigned int base;
- unsigned int size;
- unsigned int type;
-} PCI_BAR;
-
-typedef struct pciDevice {
- PCI_HOST host;
- char type[40];
- unsigned int deviceNum;
- unsigned int venID;
- unsigned int deviceID;
- PCI_BAR bar[6];
-} PCI_DEVICE;
-
-typedef struct pciSelfBars {
- unsigned int SCS0Base;
- unsigned int SCS0Size;
- unsigned int SCS1Base;
- unsigned int SCS1Size;
- unsigned int SCS2Base;
- unsigned int SCS2Size;
- unsigned int SCS3Base;
- unsigned int SCS3Size;
- unsigned int internalMemBase;
- unsigned int internalIOBase;
- unsigned int CS0Base;
- unsigned int CS0Size;
- unsigned int CS1Base;
- unsigned int CS1Size;
- unsigned int CS2Base;
- unsigned int CS2Size;
- unsigned int CS3Base;
- unsigned int CS3Size;
- unsigned int CSBootBase;
- unsigned int CSBootSize;
- unsigned int P2PMem0Base;
- unsigned int P2PMem0Size;
- unsigned int P2PMem1Base;
- unsigned int P2PMem1Size;
- unsigned int P2PIOBase;
- unsigned int P2PIOSize;
- unsigned int CPUBase;
- unsigned int CPUSize;
-} PCI_SELF_BARS;
-
-/* read/write configuration registers on local PCI bus. */
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data);
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum);
-
-/* read/write configuration registers on another PCI bus. */
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum,unsigned int data);
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum);
-
-/* Performs full scane on both PCI and returns all detail possible on the
- agents which exist on the bus. */
-void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
- unsigned int numberOfElment);
-
-/* Master`s memory space */
-bool pciMapSpace(PCI_HOST host, PCI_REGION region,
- unsigned int remapBase,
- unsigned int deviceBase,
- unsigned int deviceLength);
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
-
-/* Slave`s memory space */
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
- unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
-
-#if 0 /* GARBAGE routines - dont use till they get cleaned up */
-void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
-void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
-void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
-void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
-void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
- unsigned int pci0Dev0Length);
-void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
- unsigned int pci1Dev0Length);
-void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
- unsigned int pci0Dev1Length);
-void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
- unsigned int pci1Dev1Length);
-void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
- unsigned int pci0Dev2Length);
-void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
- unsigned int pci1Dev2Length);
-void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
- unsigned int pci0Dev3Length);
-void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
- unsigned int pci1Dev3Length);
-void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
- unsigned int pci0DevBootLength);
-void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
- unsigned int pci1DevBootLength);
-void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
- unsigned int pci0P2pMem0Length);
-void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
- unsigned int pci1P2pMem0Length);
-void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
- unsigned int pci0P2pMem1Length);
-void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
- unsigned int pci1P2pMem1Length);
-void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
- unsigned int pci0P2pIoLength);
-void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
- unsigned int pci1P2pIoLength);
-
-void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
-void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
-#endif
-
-/* PCI region options */
-
-bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength);
-
-void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
-
-/* PCI arbiter */
-
-bool pciArbiterEnable(PCI_HOST host);
-bool pciArbiterDisable(PCI_HOST host);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
- PCI_AGENT_PRIO externalAgent0,
- PCI_AGENT_PRIO externalAgent1,
- PCI_AGENT_PRIO externalAgent2,
- PCI_AGENT_PRIO externalAgent3,
- PCI_AGENT_PRIO externalAgent4,
- PCI_AGENT_PRIO externalAgent5);
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-
-/* PCI-to-PCI (P2P) */
-
-bool pciP2PConfig(PCI_HOST host,
- unsigned int SecondBusLow,unsigned int SecondBusHigh,
- unsigned int busNum,unsigned int devNum);
-/* PCI Cache-coherency */
-
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength);
-
-PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
-
-#endif /* __INCpcih */
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