diff options
| author | Marek Vasut <marex@denx.de> | 2014-08-04 01:45:46 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-08-30 07:46:39 -0400 |
| commit | 221a49d5bd4a512596c03bbc59fb28f4ef48bf6e (patch) | |
| tree | d6851c384b51ffea51470183dd063cd5dc08e30a /arch | |
| parent | a9a274c1eb51b020a4363cb99fcbebc7dc958691 (diff) | |
| download | u-boot-221a49d5bd4a512596c03bbc59fb28f4ef48bf6e.tar.gz | |
ARM: Fix overflow in MMU setup
The patch fixes a corner case where adding size to DRAM start resulted
in a value (1 << 32), which in turn overflew the u32 computation, which
resulted in 0 and it therefore prevented correct setup of the MMU tables.
The addition of DRAM bank start and it's size can end up right at the end
of the address space in the special case of a machine with enough memory.
To prevent this overflow, shift the start and size separately and add them
only after they were shifted.
Hopefully, we only have systems in tree which have DRAM size aligned to
1MiB boundary. If not, this patch would break such systems. On the other
hand, such system would be broken by design anyway.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 5fdfdbfca5..3e62d58542 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -69,7 +69,7 @@ __weak void dram_bank_mmu_setup(int bank) debug("%s: bank: %d\n", __func__, bank); for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; + i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20); i++) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) set_section_dcache(i, DCACHE_WRITETHROUGH); |