Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x

12 files changed, 272 insertions, 240 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d8b0a913be..bd97604f16 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -279,6 +279,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zc770-xm013.dtb \
 	zynq-zed.dtb \
 	zynq-zturn.dtb \
+	zynq-zturn-v5.dtb \
 	zynq-zybo.dtb \
 	zynq-zybo-z7.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
index 7826a28213..6a6e7467a2 100644
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -16,10 +16,10 @@
 	#size-cells = <2>;
 	model = "Xilinx Versal MINI eMMC0";
 
-	clk25: clk25 {
+	clk200: clk200 {
 		compatible = "fixed-clock";
 		#clock-cells = <0x0>;
-		clock-frequency = <25000000>;
+		clock-frequency = <200000000>;
 	};
 
 	dcc: dcc {
@@ -38,9 +38,12 @@
 		sdhci0: sdhci@f1040000 {
 			compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
 			status = "okay";
+			non-removable;
+			disable-wp;
+			bus-width = <8>;
 			reg = <0x0 0xf1040000 0x0 0x10000>;
 			clock-names = "clk_xin", "clk_ahb";
-			clocks = <&clk25 &clk25>;
+			clocks = <&clk200 &clk200>;
 			xlnx,device_id = <0>;
 			no-1-8-v;
 			xlnx,mio-bank = <0>;
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
index 2f28f856a6..c342e6bdf7 100644
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -16,10 +16,10 @@
 	#size-cells = <2>;
 	model = "Xilinx Versal MINI eMMC1";
 
-	clk25: clk25 {
+	clk200: clk200 {
 		compatible = "fixed-clock";
 		#clock-cells = <0x0>;
-		clock-frequency = <25000000>;
+		clock-frequency = <200000000>;
 	};
 
 	dcc: dcc {
@@ -38,9 +38,12 @@
 		sdhci1: sdhci@f1050000 {
 			compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
 			status = "okay";
+			non-removable;
+			disable-wp;
+			bus-width = <8>;
 			reg = <0x0 0xf1050000 0x0 0x10000>;
 			clock-names = "clk_xin", "clk_ahb";
-			clocks = <&clk25 &clk25>;
+			clocks = <&clk200 &clk200>;
 			xlnx,device_id = <1>;
 			no-1-8-v;
 			xlnx,mio-bank = <0>;
diff --git a/arch/arm/dts/zynq-zturn-common.dtsi b/arch/arm/dts/zynq-zturn-common.dtsi
new file mode 100644
index 0000000000..1d7af02893
--- /dev/null
+++ b/arch/arm/dts/zynq-zturn-common.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
+ *  Copyright (C) 2017 Alexander Graf <agraf@suse.de>
+ *
+ *  Based on zynq-zed.dts which is:
+ *  Copyright (C) 2011 - 2014 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+	compatible = "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart1;
+		serial1 = &uart0;
+		mmc0 = &sdhci0;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		usr-led1 {
+			label = "usr-led1";
+			gpios = <&gpio0 0x0 0x1>;
+			default-state = "off";
+		};
+
+		usr-led2 {
+			label = "usr-led2";
+			gpios = <&gpio0 0x9 0x1>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		K1 {
+			label = "K1";
+			gpios = <&gpio0 0x32 0x1>;
+			linux,code = <0x66>;
+			wakeup-source;
+			autorepeat;
+		};
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+	};
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&can0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	stlm75@49 {
+		status = "okay";
+		compatible = "lm75";
+		reg = <0x49>;
+	};
+
+	accelerometer@53 {
+		compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
+		reg = <0x53>;
+		interrupt-parent = <&intc>;
+		interrupts = <0x0 0x1e 0x4>;
+	};
+};
diff --git a/arch/arm/dts/zynq-zturn-v5.dts b/arch/arm/dts/zynq-zturn-v5.dts
new file mode 100644
index 0000000000..536632a09a
--- /dev/null
+++ b/arch/arm/dts/zynq-zturn-v5.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+/include/ "zynq-zturn-common.dtsi"
+
+/ {
+	model = "Zynq Z-Turn MYIR Board V5";
+	compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
+};
+
+&gem0 {
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0x3>;
+	};
+};
diff --git a/arch/arm/dts/zynq-zturn.dts b/arch/arm/dts/zynq-zturn.dts
index 600e8ee025..620b24a25e 100644
--- a/arch/arm/dts/zynq-zturn.dts
+++ b/arch/arm/dts/zynq-zturn.dts
@@ -1,122 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0
-/*
- *  Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
- *  Copyright (C) 2017 Alexander Graf <agraf@suse.de>
- *
- *  Based on zynq-zed.dts which is:
- *  Copyright (C) 2011 - 2014 Xilinx
- *  Copyright (C) 2012 National Instruments Corp.
- *
- */
 
 /dts-v1/;
-/include/ "zynq-7000.dtsi"
+/include/ "zynq-zturn-common.dtsi"
 
 / {
 	model = "Zynq Z-Turn MYIR Board";
 	compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
-
-	aliases {
-		ethernet0 = &gem0;
-		serial0 = &uart1;
-		serial1 = &uart0;
-		mmc0 = &sdhci0;
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x40000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-		usr-led1 {
-			label = "usr-led1";
-			gpios = <&gpio0 0x0 0x1>;
-			default-state = "off";
-		};
-
-		usr-led2 {
-			label = "usr-led2";
-			gpios = <&gpio0 0x9 0x1>;
-			default-state = "off";
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		autorepeat;
-		K1 {
-			label = "K1";
-			gpios = <&gpio0 0x32 0x1>;
-			linux,code = <0x66>;
-			wakeup-source;
-			autorepeat;
-		};
-	};
-};
-
-&clkc {
-	ps-clk-frequency = <33333333>;
-};
-
-&qspi {
-	u-boot,dm-pre-reloc;
-	status = "okay";
 };
 
 &gem0 {
-	status = "okay";
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethernet_phy>;
-
 	ethernet_phy: ethernet-phy@0 {
 		reg = <0x0>;
 	};
 };
-
-&sdhci0 {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
-&uart0 {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
-&uart1 {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-	dr_mode = "host";
-};
-
-&can0 {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <400000>;
-
-	stlm75@49 {
-		status = "okay";
-		compatible = "lm75";
-		reg = <0x49>;
-	};
-
-	accelerometer@53 {
-		compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
-		reg = <0x53>;
-		interrupt-parent = <&intc>;
-		interrupts = <0x0 0x1e 0x4>;
-	};
-};
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index a76e640466..9b4320fe6e 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -70,7 +70,7 @@
 		reg = <0x0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
-		spi-max-frequency = <108000000>;
+		spi-max-frequency = <40000000>;
 	};
 };
 
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index cb8cfd2f35..d09141c3bc 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -9,7 +9,6 @@
 #include <init.h>
 #include <log.h>
 #include <spl.h>
-#include <generated/dt.h>
 
 #include <asm/io.h>
 #include <asm/spl.h>
@@ -86,16 +85,3 @@ void spl_board_prepare_for_boot(void)
 	ps7_post_config();
 	debug("SPL bye\n");
 }
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE);
-
-	if (!strcmp(name, DEVICE_TREE))
-		return 0;
-
-	return -1;
-}
-#endif
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index f2b3ceab13..1c12eac715 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -9,6 +9,16 @@
 
 #define ZYNQMP_CSU_SILICON_VER_MASK	0xF
 #define KEY_PTR_LEN	32
+#define IV_SIZE		12
+#define RSA_KEY_SIZE	512
+#define MODULUS_LEN	512
+#define PRIV_EXPO_LEN	512
+#define PUB_EXPO_LEN	4
+
+#define ZYNQMP_SHA3_INIT	1
+#define ZYNQMP_SHA3_UPDATE	2
+#define ZYNQMP_SHA3_FINAL	4
+#define ZYNQMP_SHA3_SIZE	48
 
 #define ZYNQMP_FPGA_BIT_AUTH_DDR	1
 #define ZYNQMP_FPGA_BIT_AUTH_OCM	2
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index 9dd61e25f6..88386b23e5 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -119,13 +119,3 @@ int spl_start_uboot(void)
 	return 0;
 }
 #endif
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
-
-	return -1;
-}
-#endif
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index ff6b3c7e3d..99a17bccb3 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -16,10 +16,14 @@ config TARGET_MICROBLAZE_GENERIC
 	select OF_CONTROL
 	select SUPPORT_SPL
 	select SYSRESET
+	select DM_SPI
+	select DM_SPI_FLASH
+	select SPI
 	imply CMD_DM
 
 endchoice
 
+source "board/xilinx/Kconfig"
 source "board/xilinx/microblaze-generic/Kconfig"
 
 endmenu
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index cbec299b7d..9479737aa2 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -13,31 +13,108 @@
 	.text
 	.global _start
 _start:
-	/*
-	 * reserve registers:
-	 * r10: Stores little/big endian offset for vectors
-	 * r2: Stores imm opcode
-	 * r3: Stores brai opcode
-	 */
-
 	mts	rmsr, r0	/* disable cache */
 
 	addi	r8, r0, __end
 	mts	rslr, r8
-	/* TODO: Redo this code to call board_init_f_*() */
+
 #if defined(CONFIG_SPL_BUILD)
 	addi	r1, r0, CONFIG_SPL_STACK_ADDR
-	mts	rshr, r1
-	addi	r1, r1, -4	/* Decrement SP to top of memory */
-#else
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
-	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN)
 #else
 	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET
 #endif
-	mts	rshr, r1
+
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
 
+	/* Call board_init_f_alloc_reserve with the current stack pointer as
+	 * parameter. */
+	add	r5, r0, r1
+	bralid	r15, board_init_f_alloc_reserve
+	nop
+
+	/* board_init_f_alloc_reserve returns a pointer to the allocated area
+	 * in r3. Set the new stack pointer below this area. */
+	add	r1, r0, r3
+	mts	rshr, r1
+	addi	r1, r1, -4
+
+	/* Call board_init_f_init_reserve with the address returned by
+	 * board_init_f_alloc_reserve as parameter. */
+	add	r5, r0, r3
+	bralid	r15, board_init_f_init_reserve
+	nop
+
+#if !defined(CONFIG_SPL_BUILD)
+	/* Setup vectors with pre-relocation symbols */
+	or	r5, r0, r0
+	bralid	r15, __setup_exceptions
+	nop
+#endif
+
+	/* Flush cache before enable cache */
+	addik	r5, r0, 0
+	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
+	bralid	r15, flush_cache
+	nop
+
+	/* enable instruction and data cache */
+	mfs	r12, rmsr
+	ori	r12, r12, 0x1a0
+	mts	rmsr, r12
+
+clear_bss:
+	/* clear BSS segments */
+	addi	r5, r0, __bss_start
+	addi	r4, r0, __bss_end
+	cmp	r6, r5, r4
+	beqi	r6, 3f
+2:
+	swi     r0, r5, 0 /* write zero to loc */
+	addi    r5, r5, 4 /* increment to next loc */
+	cmp     r6, r5, r4 /* check if we have reach the end */
+	bnei    r6, 2b
+3:	/* jumping to board_init */
+#ifdef CONFIG_DEBUG_UART
+	bralid	r15, debug_uart_init
+	nop
+#endif
+#ifndef CONFIG_SPL_BUILD
+	or	r5, r0, r0	/* flags - empty */
+	brai	board_init_f
+#else
+	brai	board_init_r
+#endif
+1:	bri	1b
+
+#ifndef CONFIG_SPL_BUILD
+	.text
+	.ent	__setup_exceptions
+	.align	2
+/*
+ * Set up reset, interrupt, user exception and hardware exception vectors.
+ *
+ * Parameters:
+ * r5 - relocation offset (zero when setting up vectors before
+ *      relocation, and gd->reloc_off when setting up vectors after
+ *      relocation)
+ *    - the relocation offset is added to the _exception_handler,
+ *      _interrupt_handler and _hw_exception_handler symbols to reflect the
+ *      post-relocation memory addresses
+ *
+ * Reserve registers:
+ * r10: Stores little/big endian offset for vectors
+ * r2: Stores imm opcode
+ * r3: Stores brai opcode
+ */
+__setup_exceptions:
+	addik	r1, r1, -28
+	swi	r2, r1, 4
+	swi	r3, r1, 8
+	swi	r6, r1, 12
+	swi	r7, r1, 16
+	swi	r8, r1, 20
+	swi	r10, r1, 24
+
 	/* Find-out if u-boot is running on BIG/LITTLE endian platform
 	 * There are some steps which is necessary to keep in mind:
 	 * 1. Setup offset value to r6
@@ -76,7 +153,7 @@ _start:
 	swi	r2, r0, 0x8	/* user vector exception - imm opcode */
 	swi	r3, r0, 0xC	/* user vector exception - brai opcode */
 
-	addik	r6, r0, _exception_handler
+	addik	r6, r5, _exception_handler
 	sw	r6, r1, r0
 	/*
 	 * BIG ENDIAN memory map for user exception
@@ -109,7 +186,7 @@ _start:
 	swi	r2, r0, 0x10	/* interrupt - imm opcode */
 	swi	r3, r0, 0x14	/* interrupt - brai opcode */
 
-	addik	r6, r0, _interrupt_handler
+	addik	r6, r5, _interrupt_handler
 	sw	r6, r1, r0
 	lhu	r7, r1, r10
 	rsubi	r8, r10, 0x12
@@ -121,67 +198,26 @@ _start:
 	swi	r2, r0, 0x20	/* hardware exception - imm opcode */
 	swi	r3, r0, 0x24	/* hardware exception - brai opcode */
 
-	addik	r6, r0, _hw_exception_handler
+	addik	r6, r5, _hw_exception_handler
 	sw	r6, r1, r0
 	lhu	r7, r1, r10
 	rsubi	r8, r10, 0x22
 	sh	r7, r0, r8
 	rsubi	r8, r10, 0x26
 	sh	r6, r0, r8
-#endif /* CONFIG_SPL_BUILD */
-
-	/* Flush cache before enable cache */
-	addik	r5, r0, 0
-	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
-	bralid r15, flush_cache
-	nop
-
-	/* enable instruction and data cache */
-	mfs	r12, rmsr
-	ori	r12, r12, 0x1a0
-	mts	rmsr, r12
 
-	/* TODO: Redo this code to call board_init_f_*() */
-clear_bss:
-	/* clear BSS segments */
-	addi	r5, r0, __bss_start
-	addi	r4, r0, __bss_end
-	cmp	r6, r5, r4
-	beqi	r6, 3f
-2:
-	swi     r0, r5, 0 /* write zero to loc */
-	addi    r5, r5, 4 /* increment to next loc */
-	cmp     r6, r5, r4 /* check if we have reach the end */
-	bnei    r6, 2b
-3:	/* jumping to board_init */
-#ifdef CONFIG_DEBUG_UART
-	bralid	r15, debug_uart_init
-	nop
-#endif
-#ifndef CONFIG_SPL_BUILD
-	or	r5, r0, r0	/* flags - empty */
-	addi    r31, r0, _gd
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
-	addi	r6, r0, CONFIG_SYS_INIT_SP_OFFSET
-	swi	r6, r31, GD_MALLOC_BASE
-#endif
-	brai	board_init_f
-#else
-	addi	r31, r0, _gd
-#if CONFIG_VAL(SYS_MALLOC_F_LEN)
-	addi	r6, r0, CONFIG_SPL_STACK_ADDR
-	swi	r6, r31, GD_MALLOC_BASE
-#endif
-	brai	board_init_r
-#endif
-1:	bri	1b
+	lwi	r10, r1, 24
+	lwi	r8, r1, 20
+	lwi	r7, r1, 16
+	lwi	r6, r1, 12
+	lwi	r3, r1, 8
+	lwi	r2, r1, 4
+	addik	r1, r1, 28
 
- .section .bss
-.align 4
-_gd:
-         .space  GENERATED_GBL_DATA_SIZE
+	rtsd	r15, 8
+	or	r0, r0, r0
+	.end	__setup_exceptions
 
-#ifndef CONFIG_SPL_BUILD
 /*
  * Read 16bit little endian
  */
@@ -249,39 +285,10 @@ relocate_code:
 	addi	r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
 	rsub	r23, r24, r23 /* keep - this is already here gd->reloc_off */
 
-	addik	r6, r0, 0x2 /* BIG/LITTLE endian offset */
-	lwi	r7, r0, 0x28
-	swi	r6, r0, 0x28 /* used first unused MB vector */
-	lbui	r10, r0, 0x28 /* used first unused MB vector */
-	swi	r7, r0, 0x28
-
-#ifdef CONFIG_SYS_USR_EXCEP
-	addik	r6, r0, _exception_handler
-	addk	r6, r6, r23 /* add offset */
-	sw	r6, r1, r0
-	lhu	r7, r1, r10
-	rsubi	r8, r10, 0xa
-	sh	r7, r0, r8
-	rsubi	r8, r10, 0xe
-	sh	r6, r0, r8
-#endif
-	addik	r6, r0, _hw_exception_handler
-	addk	r6, r6, r23 /* add offset */
-	sw	r6, r1, r0
-	lhu	r7, r1, r10
-	rsubi	r8, r10, 0x22
-	sh	r7, r0, r8
-	rsubi	r8, r10, 0x26
-	sh	r6, r0, r8
-
-	addik	r6, r0, _interrupt_handler
-	addk	r6, r6, r23 /* add offset */
-	sw	r6, r1, r0
-	lhu	r7, r1, r10
-	rsubi	r8, r10, 0x12
-	sh	r7, r0, r8
-	rsubi	r8, r10, 0x16
-	sh	r6, r0, r8
+	/* Setup vectors with post-relocation symbols */
+	add	r5, r0, r23 /* load gd->reloc_off to r5 */
+	bralid	r15, __setup_exceptions
+	nop
 
 	/* Check if GOT exist */
 	addik	r21, r23, _got_start