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author | Tom Rini <trini@konsulko.com> | 2017-06-29 15:28:51 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2017-06-29 15:28:51 -0400 |
commit | f42f25dad80688886b4e0b12b8e75c86c4d350e7 (patch) | |
tree | 6a09cbb34ea3d25119ee3085327273dac6c42004 /arch | |
parent | e3f40720bac263c00b5f78777fa948775ed1330f (diff) | |
parent | 67482f57e6127d7d3e216dae6860dac7b33132d5 (diff) | |
download | u-boot-f42f25dad80688886b4e0b12b8e75c86c4d350e7.tar.gz |
Merge git://git.denx.de/u-boot-arc
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arc/Kconfig | 4 | ||||
-rw-r--r-- | arch/arc/dts/Makefile | 1 | ||||
-rw-r--r-- | arch/arc/dts/hsdk.dts | 50 | ||||
-rw-r--r-- | arch/arc/lib/cache.c | 29 | ||||
-rw-r--r-- | arch/arc/lib/start.S | 4 |
5 files changed, 82 insertions, 6 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 6e4b1d0e22..e3f9db7b29 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -132,10 +132,14 @@ config TARGET_AXS101 config TARGET_AXS103 bool "Support Synopsys Designware SDP board AXS103" +config TARGET_HSDK + bool "Support Synpsys HS DevelopmentKit board" + endchoice source "board/abilis/tb100/Kconfig" source "board/synopsys/Kconfig" source "board/synopsys/axs10x/Kconfig" +source "board/synopsys/hsdk/Kconfig" endmenu diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index 218a6475dd..63a6694712 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_AXS101) += axs101.dtb dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb +dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb targets += $(dtb-y) diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts new file mode 100644 index 0000000000..a7b276c01e --- /dev/null +++ b/arch/arc/dts/hsdk.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &uart0; + }; + + cpu_card { + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000000>; + u-boot,dm-pre-reloc; + }; + }; + + uart0: serial0@f0005000 { + compatible = "snps,dw-apb-uart"; + reg = <0xf0005000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + ethernet@f0008000 { + #interrupt-cells = <1>; + compatible = "altr,socfpga-stmmac"; + reg = <0xf0008000 0x2000>; + phy-mode = "gmii"; + }; + + ehci@0xf0040000 { + compatible = "generic-ehci"; + reg = <0xf0040000 0x100>; + }; + + ohci@0xf0060000 { + compatible = "generic-ohci"; + reg = <0xf0060000 0x100>; + }; +}; diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index f1436bf199..cbae27e9fc 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -8,6 +8,7 @@ #include <common.h> #include <linux/compiler.h> #include <linux/kernel.h> +#include <linux/log2.h> #include <asm/arcregs.h> #include <asm/cache.h> @@ -215,17 +216,33 @@ void cache_init(void) read_decode_cache_bcr_arcv2(); if (ioc_exists) { + /* IOC Aperture start is equal to DDR start */ + unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + /* IOC Aperture size is equal to DDR size */ + long ap_size = CONFIG_SYS_SDRAM_SIZE; + flush_dcache_all(); invalidate_dcache_all(); - /* IO coherency base - 0x8z */ - write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000); - /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ - write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 0x11); - /* Enable partial writes */ + if (!is_power_of_2(ap_size) || ap_size < 4096) + panic("IOC Aperture size must be power of 2 and bigger 4Kib"); + + /* + * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, + * so setting 0x11 implies 512M, 0x12 implies 1G... + */ + write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, + order_base_2(ap_size/1024) - 2); + + + /* IOC Aperture start must be aligned to the size of the aperture */ + if (ap_base % ap_size != 0) + panic("IOC Aperture start must be aligned to the size of the aperture"); + + write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); - /* Enable IO coherency */ write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); + } #endif } diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index b2ba768309..95d64f9d43 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -10,6 +10,9 @@ #include <asm/arcregs.h> ENTRY(_start) +; ARCompact devices are not supposed to be SMP so master/slave check +; makes no sense. +#ifdef CONFIG_ISA_ARCV2 ; Non-masters will be halted immediately, they might be kicked later ; by platform code right before passing control to the Linux kernel ; in bootm.c:boot_jump_linux(). @@ -25,6 +28,7 @@ ENTRY(_start) nop .Lmaster_proceed: +#endif /* Setup interrupt vector base that matches "__text_start" */ sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] |