Merge git://git.denx.de/u-boot-uniphier

5 files changed, 36 insertions, 29 deletions

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index ee22112412..c8b5ab4d32 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -12,18 +12,14 @@ config ARCH_UNIPHIER_32BIT
 
 choice
         prompt "UniPhier SoC select"
-        default ARCH_UNIPHIER_PRO4
+        default ARCH_UNIPHIER_V8_MULTI
 
 config ARCH_UNIPHIER_LD4_SLD8
 	bool "UniPhier LD4/sLD8 SoCs"
 	select ARCH_UNIPHIER_32BIT
 
-config ARCH_UNIPHIER_PRO4
-	bool "UniPhier Pro4 SoC"
-	select ARCH_UNIPHIER_32BIT
-
-config ARCH_UNIPHIER_PRO5_PXS2_LD6B
-	bool "UniPhier Pro5/PXs2/LD6b SoCs"
+config ARCH_UNIPHIER_V7_MULTI
+	bool "UniPhier Pro4/Pro5/PXs2/LD6b SoCs"
 	select ARCH_UNIPHIER_32BIT
 
 config ARCH_UNIPHIER_V8_MULTI
@@ -44,19 +40,24 @@ config ARCH_UNIPHIER_SLD8
 	depends on ARCH_UNIPHIER_LD4_SLD8
 	default y
 
+config ARCH_UNIPHIER_PRO4
+	bool "Enable UniPhier Pro4 SoC support"
+	depends on ARCH_UNIPHIER_V7_MULTI
+	default y
+
 config ARCH_UNIPHIER_PRO5
 	bool "Enable UniPhier Pro5 SoC support"
-	depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+	depends on ARCH_UNIPHIER_V7_MULTI
 	default y
 
 config ARCH_UNIPHIER_PXS2
 	bool "Enable UniPhier Pxs2 SoC support"
-	depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+	depends on ARCH_UNIPHIER_V7_MULTI
 	default y
 
 config ARCH_UNIPHIER_LD6B
 	bool "Enable UniPhier LD6b SoC support"
-	depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+	depends on ARCH_UNIPHIER_V7_MULTI
 	default y
 
 config ARCH_UNIPHIER_LD11
diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
index 0266e7e66b..a4b7419e54 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld11.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -40,7 +40,7 @@ void uniphier_ld11_clk_init(void)
 		int ch;
 
 		tmp = readl(SC_CLKCTRL4);
-		tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
+		tmp |= BIT(10) | BIT(8);	/* MIO, STDMAC */
 		writel(tmp, SC_CLKCTRL4);
 
 		for (ch = 0; ch < 3; ch++) {
diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c
index 5bb560cafe..f79fb38535 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld20.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld20.c
@@ -4,14 +4,26 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/bitops.h>
 #include <linux/io.h>
 
 #include "../init.h"
+#include "../sc64-regs.h"
 
 #define SDCTRL_EMMC_HW_RESET	0x59810280
 
 void uniphier_ld20_clk_init(void)
 {
+	u32 tmp;
+
+	tmp = readl(SC_RSTCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, SC_RSTCTRL6);
+
+	tmp = readl(SC_CLKCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, SC_CLKCTRL6);
+
 	/* TODO: use "mmc-pwrseq-emmc" */
 	writel(1, SDCTRL_EMMC_HW_RESET);
 }
diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c
index 2dee857a18..3b9cc626f1 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c
@@ -4,14 +4,26 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/bitops.h>
 #include <linux/io.h>
 
 #include "../init.h"
+#include "../sc64-regs.h"
 
 #define SDCTRL_EMMC_HW_RESET	0x59810280
 
 void uniphier_pxs3_clk_init(void)
 {
+	u32 tmp;
+
+	tmp = readl(SC_RSTCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, SC_RSTCTRL6);
+
+	tmp = readl(SC_CLKCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, SC_CLKCTRL6);
+
 	/* TODO: use "mmc-pwrseq-emmc" */
 	writel(1, SDCTRL_EMMC_HW_RESET);
 }
diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index d0a51f239c..80efb4e4e3 100644
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -15,34 +15,16 @@
 #define SC_RSTCTRL		(SC_BASE_ADDR | 0x2000)
 #define SC_RSTCTRL3		(SC_BASE_ADDR | 0x2008)
 #define SC_RSTCTRL4		(SC_BASE_ADDR | 0x200c)
-#define   SC_RSTCTRL4_ETHER		(1 << 6)
-#define   SC_RSTCTRL4_NAND		(1 << 0)
 #define SC_RSTCTRL5		(SC_BASE_ADDR | 0x2010)
 #define SC_RSTCTRL6		(SC_BASE_ADDR | 0x2014)
 #define SC_RSTCTRL7		(SC_BASE_ADDR | 0x2018)
-#define   SC_RSTCTRL7_UMCSB		(1 << 16)
-#define   SC_RSTCTRL7_UMCA2		(1 << 10)
-#define   SC_RSTCTRL7_UMCA1		(1 << 9)
-#define   SC_RSTCTRL7_UMCA0		(1 << 8)
-#define   SC_RSTCTRL7_UMC32		(1 << 2)
-#define   SC_RSTCTRL7_UMC31		(1 << 1)
-#define   SC_RSTCTRL7_UMC30		(1 << 0)
 
 #define SC_CLKCTRL		(SC_BASE_ADDR | 0x2100)
 #define SC_CLKCTRL3		(SC_BASE_ADDR | 0x2108)
 #define SC_CLKCTRL4		(SC_BASE_ADDR | 0x210c)
-#define   SC_CLKCTRL4_MIO		(1 << 10)
-#define   SC_CLKCTRL4_STDMAC		(1 << 8)
-#define   SC_CLKCTRL4_PERI		(1 << 7)
-#define   SC_CLKCTRL4_ETHER		(1 << 6)
-#define   SC_CLKCTRL4_NAND		(1 << 0)
 #define SC_CLKCTRL5		(SC_BASE_ADDR | 0x2110)
 #define SC_CLKCTRL6		(SC_BASE_ADDR | 0x2114)
 #define SC_CLKCTRL7		(SC_BASE_ADDR | 0x2118)
-#define   SC_CLKCTRL7_UMCSB		(1 << 16)
-#define   SC_CLKCTRL7_UMC32		(1 << 2)
-#define   SC_CLKCTRL7_UMC31		(1 << 1)
-#define   SC_CLKCTRL7_UMC30		(1 << 0)
 
 #define SC_CA72_GEARST		(SC_BASE_ADDR | 0x8000)
 #define SC_CA72_GEARSET		(SC_BASE_ADDR | 0x8004)