diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-08-14 21:33:01 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-08-26 17:04:56 -0400 |
| commit | 8f894a4d38adff26733225fb170f2a2d3e2b3054 (patch) | |
| tree | ce5df402c6be75e7db1883b2eae3cc2a2fbd8bf9 /arch | |
| parent | c5b3cabf4a2f78b126a7da92c20b781a52d5307f (diff) | |
| download | u-boot-8f894a4d38adff26733225fb170f2a2d3e2b3054.tar.gz | |
arm: cache: always flush cache line size for page table
The page table is maintained by the CPU, hence it is safe to always
align cache flush to a whole cache line size. This allows to use
mmu_page_table_flush for a single page table, e.g. when configure
only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 3aabda156b..70e94f03a4 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -66,6 +66,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, #else u32 *page_table = (u32 *)gd->arch.tlb_addr; #endif + unsigned long startpt, stoppt; unsigned long upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; @@ -74,7 +75,18 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option); - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); + + /* + * Make sure range is cache line aligned + * Only CPU maintains page tables, hence it is safe to always + * flush complete cache lines... + */ + + startpt = (unsigned long)&page_table[start]; + startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); + stoppt = (unsigned long)&page_table[end]; + stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); + mmu_page_table_flush(startpt, stoppt); } __weak void dram_bank_mmu_setup(int bank) |