diff options
| author | Marek Vasut <marex@denx.de> | 2018-05-29 18:02:22 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-07-12 09:22:13 +0200 |
| commit | df78f016e84caede20938fb3e84acbb8ae7fc440 (patch) | |
| tree | b71f91bea7ec35750f036cbab7648de609a35f4b /arch | |
| parent | 297b653bbffe4e3bcc9534d70bd92e11545a7c4a (diff) | |
| download | u-boot-df78f016e84caede20938fb3e84acbb8ae7fc440.tar.gz | |
ARM: socfpga: Make DRAM node available in SPL
The SPL can also parse the DRAM configuration node to figure out the
memory layout, make sure it is available.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/socfpga_arria10_socdk.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index d7616dd1c5..3f59f02577 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -34,6 +34,7 @@ name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ + u-boot,dm-pre-reloc; }; a10leds { |