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author | Tom Rini <trini@konsulko.com> | 2020-09-25 09:04:01 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2020-09-25 09:04:01 -0400 |
commit | 0ac83d080a0044cd0d8f782ba12f02cf969d3004 (patch) | |
tree | ca5c2351113ba9b56d59e241a8857c7e6e8f5604 /arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl | |
parent | 67ece26d8b5d4bfa4fda8c456261c465d0815d7d (diff) | |
parent | 8c180d669a0f4a8eb70bde8c74c73cef45993f67 (diff) | |
download | u-boot-0ac83d080a0044cd0d8f782ba12f02cf969d3004.tar.gz |
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into nextWIP/25Sep2020-next
- Enhance the 'zboot' command to be more like 'bootm' with sub-commands
- The last series of ACPI core changes for programmatic generation of
ACPI tables
- Add all required ACPI tables for ApolloLake and enable ACPIGEN on
Chromebook Coral
- A feature minor enhancements to the 'hob' command
- Intel edison: Support for writing an xFSTK image via binman
Diffstat (limited to 'arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl')
-rw-r--r-- | arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl new file mode 100644 index 0000000000..12a08b4aa8 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation + */ + +/* Include in each PCIe Root Port device */ + +/* lowest D-state supported by + * PCIe root port during S0 state + */ +Name (_S0W, 4) + +Name (PDST, 0) /* present Detect status */ + +/* Dynamic Opregion needed to access registers + * when the controller is in D3 cold + */ +OperationRegion (PX01, PCI_Config, 0x00, 0xFF) +Field (PX01, AnyAcc, NoLock, Preserve) +{ + Offset(0x5A), + , 6, + PDS, 1, /* 6, Presence detect Change */ + Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ + Offset(0xF4), /* BLKPLLEN */ + , 10, + BPLL, 1, +} + +OperationRegion (PX02, PCI_Config, 0x338, 0x4) +Field (PX02, AnyAcc, NoLock, Preserve) +{ + , 26, + BDQA, 1 /* BLKDQDA */ +} + +PowerResource (PXP, 0, 0) +{ + /* Define the PowerResource for PCIe slot */ + Method (_STA, 0, Serialized) + { + Store (PDS, PDST) + If (LEqual (PDS, 1)) { + Return (0xf) + } Else { + Return (0) + } + } + + Method (_ON, 0, Serialized) + { + If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + /* Enter this condition if device + * is connected + */ + + /* De-assert PERST */ + \_SB.PCI0.PRDA (\PRT0) + + Store (0, BDQA) /* Set BLKDQDA to 0 */ + Store (0, BPLL) /* Set BLKPLLEN to 0 */ + + /* Set L23_Rdy to Detect Transition + * (L23R2DT) + */ + Store (1, L23R) + Sleep (16) + Store (0, Local0) + + /* Delay for transition Detect + * and link to train + */ + While (L23R) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + } /* End PDS condition check */ + } + + Method (_OFF, 0, Serialized) + { + /* Set L23_Rdy Entry Request (L23ER) */ + If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + /* enter this condition if device + * is connected + */ + Store (1, L23E) + Sleep (16) + Store (0, Local0) + While (L23E) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + Store (1, BDQA) /* Set BLKDQDA to 1 */ + Store (1, BPLL) /* Set BLKPLLEN to 1 */ + + /* Assert PERST */ + \_SB.PCI0.PRAS (\PRT0) + } /* End PDS condition check */ + } /* End of Method_OFF */ +} /* End PXP */ + +Name(_PR0, Package() { PXP }) +Name(_PR3, Package() { PXP }) |