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| author | Simon Glass <sjg@chromium.org> | 2015-01-19 22:16:14 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-01-24 06:13:45 -0700 |
| commit | 191c008a2155f99fc6476539878640b4032a457b (patch) | |
| tree | 36823854ae5d3de1b03646f7d8230df51a62743e /arch/x86/cpu/ivybridge/Makefile | |
| parent | a9aff2f46a7f7d29a662531dbc181773f16a606d (diff) | |
| download | u-boot-191c008a2155f99fc6476539878640b4032a457b.tar.gz | |
x86: Implement a cache for Memory Reference Code parameters
The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.
Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/ivybridge/Makefile')
| -rw-r--r-- | arch/x86/cpu/ivybridge/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 0c7efaec7c..3576b83266 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -14,6 +14,7 @@ obj-y += lpc.o obj-y += me_status.o obj-y += model_206ax.o obj-y += microcode_intel.o +obj-y += mrccache.o obj-y += northbridge.o obj-y += pch.o obj-y += pci.o |