diff options
| author | Sean Anderson <seanga2@gmail.com> | 2020-09-21 07:51:41 -0400 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-09-30 08:54:52 +0800 |
| commit | 924de3216e9efdf1cdc71b8632099213aac03f2c (patch) | |
| tree | b75fb39f6c9eb05808bb17567c31edc617259096 /arch/riscv | |
| parent | 85768134b40794a108a2dafb4a565b712e359c46 (diff) | |
| download | u-boot-924de3216e9efdf1cdc71b8632099213aac03f2c.tar.gz | |
riscv: Add some comments to start.S
This adds comments regarding the ordering and purpose of certain
instructions as I understand them.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index eb852538ca..bbc737ed9a 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -43,7 +43,10 @@ _start: csrr a0, CSR_MHARTID #endif - /* save hart id and dtb pointer */ + /* + * Save hart id and dtb pointer. The thread pointer register is not + * modified by C code. It is used by secondary_hart_loop. + */ mv tp, a0 mv s1, a1 @@ -54,10 +57,18 @@ _start: */ mv gp, zero + /* + * Set the trap handler. This must happen after initializing gp because + * the handler may use it. + */ la t0, trap_entry csrw MODE_PREFIX(tvec), t0 - /* mask all interrupts */ + /* + * Mask all interrupts. Interrupts are disabled globally (in m/sstatus) + * for U-Boot, but we will need to read m/sip to determine if we get an + * IPI + */ csrw MODE_PREFIX(ie), zero #if CONFIG_IS_ENABLED(SMP) @@ -412,6 +423,10 @@ secondary_hart_relocate: mv gp, a2 #endif +/* + * Interrupts are disabled globally, but they can still be read from m/sip. The + * wfi function will wake us up if we get an IPI, even if we do not trap. + */ secondary_hart_loop: wfi |