diff options
| author | Trevor Woerner <trevor@toganlabs.com> | 2019-05-03 09:41:00 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-18 08:15:35 -0400 |
| commit | 1001502545ff0125c39232cf0e7f26d9213ab55f (patch) | |
| tree | 6513e23c1df21e1a4bc55eb98a73a58f269ccf46 /arch/riscv | |
| parent | a0aba8a2ebae51287fbee6848aece71655795fdb (diff) | |
| download | u-boot-1001502545ff0125c39232cf0e7f26d9213ab55f.tar.gz | |
CONFIG_SPL_SYS_[DI]CACHE_OFF: add
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Kconfig | 14 | ||||
| -rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 8 |
2 files changed, 18 insertions, 4 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c993809a6a..0d04d91ad4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -25,12 +25,26 @@ config SYS_ICACHE_OFF help Do not enable instruction cache in U-Boot. +config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default SYS_ICACHE_OFF + help + Do not enable instruction cache in SPL. + config SYS_DCACHE_OFF bool "Do not enable dcache" default n help Do not enable data cache in U-Boot. +config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default SYS_DCACHE_OFF + help + Do not enable data cache in SPL. + # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 228fc55f56..cd95058d9d 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -30,7 +30,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) void icache_enable(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -43,7 +43,7 @@ void icache_enable(void) void icache_disable(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "fence.i\n\t" @@ -57,7 +57,7 @@ void icache_disable(void) void dcache_enable(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -70,7 +70,7 @@ void dcache_enable(void) void dcache_disable(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "fence\n\t" |