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| author | Bin Meng <bmeng.cn@gmail.com> | 2021-06-15 13:45:57 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-06-17 09:39:46 +0800 |
| commit | 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54 (patch) | |
| tree | 086819c8f5cbcab23e7932ab7d9aa747d3aed8e1 /arch/riscv/lib | |
| parent | 279de759bd2ceb1dad6ff30c7d27c8ff9c5706a3 (diff) | |
| download | u-boot-62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54.tar.gz | |
riscv: andes_plic: Fix riscv_get_ipi() mask
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/andes_plic.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 221a5fe324..5e113ee8c9 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { + unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart)); - *pending = !!(*pending & SEND_IPI_TO_HART(hart)); + *pending = !!(*pending & ipi); return 0; } |