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authorRick Chen <rick@andestech.com>2019-04-02 15:56:39 +0800
committerAndes <uboot@andestech.com>2019-04-08 09:45:08 +0800
commit0d389468e2144f3ba3bdbc566c05c0c05dc14fc6 (patch)
treeb48b25b552a66db5d7e92dd23bdacf82484ddd41 /arch/riscv/include/asm/global_data.h
parentd0a8fd3e4d2a5ab19b8f2d27d40dacb4942ba5a4 (diff)
downloadu-boot-0d389468e2144f3ba3bdbc566c05c0c05dc14fc6.tar.gz
riscv: Add a SYSCON driver for Andestech's PLIC
The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/include/asm/global_data.h')
-rw-r--r--arch/riscv/include/asm/global_data.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 80e3165e39..b86791094b 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,6 +18,9 @@ struct arch_global_data {
#ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint; /* clint base address */
#endif
+#ifdef CONFIG_ANDES_PLIC
+ void __iomem *plic; /* plic base address */
+#endif
#ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif