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| author | Tom Rini <trini@konsulko.com> | 2020-07-02 09:53:34 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-02 09:53:34 -0400 |
| commit | 785195941b0746ac987a0ca501dae3e570b9f042 (patch) | |
| tree | 317f4d937fb80de27123a1d18adc29ad5bf9337c /arch/riscv/cpu/cpu.c | |
| parent | e2a4d24e6b1f3d30136e2dde7b6fbf35bd427b8a (diff) | |
| parent | add0dc1f7de91112d9e738f9482b09b75fa86acb (diff) | |
| download | u-boot-WIP/02Jul2020-next.tar.gz | |
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into nextWIP/02Jul2020-next
- Add Sipeed Maix support
- Update clock handler and proper cpu features
Diffstat (limited to 'arch/riscv/cpu/cpu.c')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 5804aa8e73..bbd6c15352 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -91,13 +91,28 @@ int arch_cpu_init_dm(void) * Enable perf counters for cycle, time, * and instret counters only */ +#ifdef CONFIG_RISCV_PRIV_1_9 + csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); +#else csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); +#endif /* Disable paging */ if (supports_extension('s')) +#ifdef CONFIG_RISCV_PRIV_1_9 + csr_read_clear(CSR_MSTATUS, SR_VM); +#else csr_write(CSR_SATP, 0); +#endif } +#ifdef CONFIG_SMP + ret = riscv_init_ipi(); + if (ret) + return ret; +#endif + return 0; } |