powerpc: mpc85xx: Set TEXT_BASE addresses to real base values

Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are
manually increased by 0x1000 due to .bootpg section. This section has size
of 0x1000 bytes and is manually put by linker script before .text section
(and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is
set. Due to this fact lot of other config options are manually increased by
0x1000 value to make correct layout. Note that entry point is not on
CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address
CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image).

Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is
set. Put .bootpg code directly into .text section and move text base
address to the start of .bootpg code. And finally remove +0x1000 value from
lot of config options. With this removal custom PHDRS is not used anymore,
so remove it too.

After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at
address -0x1000 anymore.

Tested on P2020 board with SPL and proper U-Boot.

Signed-off-by: Pali Rohár <pali@kernel.org>

3 files changed, 12 insertions, 31 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 9a28269020..5009cbef54 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1128,7 +1128,7 @@ switch_as:
 	/*--------------------------------------------------------------*/
 	lis	r3,CONFIG_VAL(SYS_MONITOR_BASE)@h
 	ori	r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l
-	addi	r3,r3,_start_cont - _start_cont
+	addi	r3,r3,_start_cont - CONFIG_VAL(SYS_MONITOR_BASE)
 	mtlr	r3
 	blr
 #endif
@@ -1600,7 +1600,7 @@ relocate_code:
  * initialization, now running from RAM.
  */
 
-	addi	r0,r10,in_ram - _start_cont
+	addi	r0,r10,in_ram - CONFIG_VAL(SYS_MONITOR_BASE)
 
 	/*
 	 * As IVPR is going to point RAM address,
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 06a70ff2af..b8e08880bd 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -9,24 +9,15 @@
 #include "config.h"
 
 OUTPUT_ARCH(powerpc)
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
-PHDRS
-{
-	text PT_LOAD;
-	bss PT_LOAD;
-}
-#endif
+
 SECTIONS
 {
+	. = IMAGE_TEXT_BASE;
+	.text : {
 /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
 #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
-	.bootpg IMAGE_TEXT_BASE - 0x1000 :
-	{
 		KEEP(*(.bootpg))
-	} :text = 0xffff
 #endif
-	. = IMAGE_TEXT_BASE;
-	.text : {
 		*(.text*)
 	}
 	_etext = .;
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 8bbe319b3e..4e137e006f 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -14,32 +14,22 @@
 OUTPUT_ARCH(powerpc)
 ENTRY(_start)
 
-PHDRS
-{
-  text PT_LOAD;
-  bss PT_LOAD;
-}
-
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
-#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
-  .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 :
+  .text      :
   {
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
     KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
-  } :text = 0xffff
-  . = CONFIG_SYS_TEXT_BASE;
 #endif
-  .text      :
-  {
     *(.text*)
-   } :text
+  }
     _etext = .;
     PROVIDE (etext = .);
     .rodata    :
    {
     *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  } :text
+  }
 
   /* Read-write section, merged into data segment: */
   . = (. + 0x00FF) & 0xFFFFFF00;
@@ -88,12 +78,12 @@ SECTIONS
   .bootpg RESET_VECTOR_ADDRESS - 0xffc :
   {
     arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
-  } :text = 0xffff
+  } = 0xffff
 
   .resetvec RESET_VECTOR_ADDRESS :
   {
     KEEP(*(.resetvec))
-  } :text = 0xffff
+  } = 0xffff
 
   . = RESET_VECTOR_ADDRESS + 0x4;
 
@@ -115,7 +105,7 @@ SECTIONS
    *(.sbss*)
    *(.bss*)
    *(COMMON)
-  } :bss
+  }
 
   . = ALIGN(4);
   __bss_end = . ;