diff options
author | Tom Rini <trini@konsulko.com> | 2021-05-23 10:58:05 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-07-07 19:52:24 -0400 |
commit | ec6b37cef4baf53a5c542c6e77e4b4433ad99f58 (patch) | |
tree | adc5eaf24f6fe952a586ffd151adac5a2ab6fc20 /arch/powerpc/include/asm/immap_85xx.h | |
parent | 1567e3255d5c850ae953d46dd6b3f42531f8d5f1 (diff) | |
download | u-boot-ec6b37cef4baf53a5c542c6e77e4b4433ad99f58.tar.gz |
ppc: Remove T4160RDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_T4160 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/powerpc/include/asm/immap_85xx.h')
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 70112c91fc..f539c0be71 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1757,7 +1757,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) +#if defined(CONFIG_ARCH_T4240) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1869,7 +1869,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) +#if defined(CONFIG_ARCH_T4240) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 |