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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-08-20 09:35:32 +0000 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-08-26 21:29:01 +0530 |
| commit | 23975db5e9979f39f997c5acbce88342e6829f71 (patch) | |
| tree | 4354e3515565c4f847e2539ce9e8909c489cadbf /arch/powerpc/dts | |
| parent | bebc0727fe24164c5bb3d969a5680f4d81a1fd4f (diff) | |
| download | u-boot-23975db5e9979f39f997c5acbce88342e6829f71.tar.gz | |
powerpc: Enable device tree support for P4080DS
Add device tree for P4080DS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/powerpc/dts')
| -rw-r--r-- | arch/powerpc/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/powerpc/dts/p4080.dtsi | 83 | ||||
| -rw-r--r-- | arch/powerpc/dts/p4080ds.dts | 18 |
3 files changed, 102 insertions, 0 deletions
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index fe2d4e40dd..ffd929c2ba 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb +dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi new file mode 100644 index 0000000000..7c8dbae442 --- /dev/null +++ b/arch/powerpc/dts/p4080.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P4080/P4040 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500mc_power_isa.dtsi" + +/ { + compatible = "fsl,P4080"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e500mc@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e500mc@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e500mc@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e500mc@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + cpu4: PowerPC,e500mc@4 { + device_type = "cpu"; + reg = <4>; + fsl,portid-mapping = <0x08000000>; + }; + cpu5: PowerPC,e500mc@5 { + device_type = "cpu"; + reg = <5>; + fsl,portid-mapping = <0x04000000>; + }; + cpu6: PowerPC,e500mc@6 { + device_type = "cpu"; + reg = <6>; + fsl,portid-mapping = <0x02000000>; + }; + cpu7: PowerPC,e500mc@7 { + device_type = "cpu"; + reg = <7>; + fsl,portid-mapping = <0x01000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts new file mode 100644 index 0000000000..15a0f66fb6 --- /dev/null +++ b/arch/powerpc/dts/p4080ds.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P4080DS Device Tree Source + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p4080.dtsi" + +/ { + model = "fsl,P4080DS"; + compatible = "fsl,P4080DS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; |