diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-08-27 11:04:04 +0000 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-08-28 13:47:46 +0530 |
| commit | 594708dd9dc9f1204ae0ea236d00e57fd25ddf0d (patch) | |
| tree | 57d226ef9d2b24d045e8ed635ef70c06c50c9b4e /arch/powerpc/dts/p1020-post.dtsi | |
| parent | ba827365f7e1ad7546e6ec3098221ebd1bcfaf27 (diff) | |
| download | u-boot-594708dd9dc9f1204ae0ea236d00e57fd25ddf0d.tar.gz | |
P1020: dts: Added PCIe DT nodes
P1020 integrated 2 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/powerpc/dts/p1020-post.dtsi')
| -rw-r--r-- | arch/powerpc/dts/p1020-post.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index e1a4f500a6..1e5e67804b 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -25,3 +25,23 @@ last-interrupt-source = <255>; }; }; + +/* PCIe controller base address 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; |