ppc: Remove MPC8569MDS boardWIP/2021-02-25-remove-platforms

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is the last ARCH_MPC8569 board, remove that support
as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

5 files changed, 2 insertions, 123 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 870ab800e8..6f90518927 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -64,10 +64,6 @@ config TARGET_MPC8568MDS
 	bool "Support MPC8568MDS"
 	select ARCH_MPC8568
 
-config TARGET_MPC8569MDS
-	bool "Support MPC8569MDS"
-	select ARCH_MPC8569
-
 config TARGET_P1010RDB_PA
 	bool "Support P1010RDB_PA"
 	select ARCH_P1010
@@ -473,19 +469,6 @@ config ARCH_MPC8568
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 
-config ARCH_MPC8569
-	bool
-	select FSL_LAW
-	select SYS_FSL_ERRATUM_A004508
-	select SYS_FSL_ERRATUM_A005125
-	select FSL_PCIE_RESET
-	select SYS_FSL_HAS_DDR3
-	select SYS_FSL_HAS_SEC
-	select SYS_FSL_SEC_BE
-	select SYS_FSL_SEC_COMPAT_2
-	select FSL_ELBC
-	imply CMD_NAND
-
 config ARCH_MPC8572
 	bool
 	select FSL_LAW
@@ -1102,7 +1085,6 @@ config SYS_CCSRBAR_DEFAULT
 				ARCH_MPC8555	|| \
 				ARCH_MPC8560	|| \
 				ARCH_MPC8568	|| \
-				ARCH_MPC8569	|| \
 				ARCH_MPC8572	|| \
 				ARCH_P1010	|| \
 				ARCH_P1011	|| \
@@ -1335,8 +1317,7 @@ config SYS_FSL_NUM_LAWS
 			ARCH_P2020
 	default 10 if	ARCH_MPC8544	|| \
 			ARCH_MPC8548	|| \
-			ARCH_MPC8568	|| \
-			ARCH_MPC8569
+			ARCH_MPC8568
 	default 8 if	ARCH_MPC8540	|| \
 			ARCH_MPC8541	|| \
 			ARCH_MPC8555	|| \
@@ -1433,7 +1414,6 @@ source "board/freescale/mpc8541cds/Kconfig"
 source "board/freescale/mpc8548cds/Kconfig"
 source "board/freescale/mpc8555cds/Kconfig"
 source "board/freescale/mpc8568mds/Kconfig"
-source "board/freescale/mpc8569mds/Kconfig"
 source "board/freescale/p1010rdb/Kconfig"
 source "board/freescale/p1_p2_rdb_pc/Kconfig"
 source "board/freescale/p2041rdb/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 019fce6314..14e46626f3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -65,7 +65,6 @@ obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
 obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
 obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
 obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
-obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
 obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
 obj-$(CONFIG_ARCH_P1010)	+= p1010_serdes.o
 obj-$(CONFIG_ARCH_P1011)	+= p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
deleted file mode 100644
index eb54b8252b..0000000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES		4
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
-	[0x0] = {PCIE1, NONE, NONE, NONE},
-	[0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
-	[0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
-	[0x3] = {SRIO1, SRIO2, NONE, NONE},
-	[0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2},
-	[0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
-	[0x6] = {PCIE1, NONE, SRIO1, SRIO2},
-	[0x7] = {PCIE1, PCIE1, SRIO1, SRIO2},
-	[0x8] = {PCIE1, PCIE1, SRIO1, SRIO2},
-	[0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
-	[0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
-	[0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
-	[0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2},
-	[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
-	if (!(serdes1_prtcl_map & (1 << NONE)))
-		fsl_serdes_init();
-
-	return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 pordevsr = in_be32(&gur->pordevsr);
-	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
-				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
-	int lane;
-
-	if (serdes1_prtcl_map & (1 << NONE))
-		return;
-
-	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
-	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
-		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
-		return;
-	}
-
-	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
-		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
-		serdes1_prtcl_map |= (1 << lane_prtcl);
-	}
-
-	/* Set the first bit to indicate serdes has been initialized */
-	serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 09653c7012..9c89ce5d70 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -630,7 +630,7 @@ int get_clocks(void)
 	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
-#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
+#if defined(CONFIG_ARCH_P1010)
 	gd->arch.sdhc_clk = gd->bus_clk;
 #else
 	gd->arch.sdhc_clk = gd->bus_clk / 2;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index dd784e7e30..f41e82ad18 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -344,39 +344,6 @@ l2_disabled:
 	mtspr	DBCR0,r0
 #endif
 
-#ifdef CONFIG_ARCH_MPC8569
-#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
-#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
-
-	/* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
-	 * use address space which is more than 12bits, and it must be done in
-	 * the 4K boot page. So we set this bit here.
-	 */
-
-	/* create a temp mapping TLB0[0] for LBCR  */
-	create_tlb0_entry 0, \
-		0, BOOKE_PAGESZ_4K, \
-		CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
-		CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
-		0, r6
-
-	/* Set LBCR register */
-	lis     r4,CONFIG_SYS_LBCR_ADDR@h
-	ori     r4,r4,CONFIG_SYS_LBCR_ADDR@l
-
-	lis     r5,CONFIG_SYS_LBC_LBCR@h
-	ori     r5,r5,CONFIG_SYS_LBC_LBCR@l
-	stw     r5,0(r4)
-	isync
-
-	/* invalidate this temp TLB */
-	lis	r4,CONFIG_SYS_LBC_ADDR@h
-	ori	r4,r4,CONFIG_SYS_LBC_ADDR@l
-	tlbivax	0,r4
-	isync
-
-#endif /* CONFIG_ARCH_MPC8569 */
-
 /*
  * Search for the TLB that covers the code we're executing, and shrink it
  * so that it covers only this 4K page.  That will ensure that any other