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| author | York Sun <yorksun@freescale.com> | 2012-05-07 07:26:45 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-07-06 17:30:33 -0500 |
| commit | 1e9ea85f7dffe949ca5e4845e6336810c144e06d (patch) | |
| tree | b0dd4cf4a6f7cb05031c67242660fcfac0af8fcb /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | 7b6e80538b919c814c94ce8887cec7b892f98a71 (diff) | |
| download | u-boot-1e9ea85f7dffe949ca5e4845e6336810c144e06d.tar.gz | |
powerpc/P4080: Check SVR for CPU22 workaround
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index c81e19c0e9..fe3b6d6cbc 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -144,9 +144,17 @@ __secondary_start_page: #endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) + /* apply to P4080 rev 1 and rev 2 */ + mfspr r3,SPRN_SVR + rlwinm r3,r3,0,0xf0 + li r4,0x30 + cmpw r3,r4 + bge 2f + mfspr r8,L1CSR2 oris r8,r8,(L1CSR2_DCWS)@h mtspr L1CSR2,r8 +2: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE |