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authorTom Rini <trini@konsulko.com>2019-05-04 20:02:31 -0400
committerTom Rini <trini@konsulko.com>2019-05-04 20:02:42 -0400
commit86f578ee85a697afb980233312f9aac1d98816df (patch)
treec15c40d7885eac1dff3bdd1e3236e9d42e26c820 /arch/mips/mach-mtmips/mt76xx.h
parentc9baea6d0e96eb4bf55061d516e91e22236ed198 (diff)
parent5c629b1b69f780540e6e3bcc57d29438749f97c5 (diff)
downloadu-boot-86f578ee85a697afb980233312f9aac1d98816df.tar.gz
Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mips
- mscc: small fixes, enhance network support for Serval, Luton and Ocelot - mt7620: rename arch to more generic name mtmips - mips: pass initrd addresses via DT as physical addresses
Diffstat (limited to 'arch/mips/mach-mtmips/mt76xx.h')
-rw-r--r--arch/mips/mach-mtmips/mt76xx.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/mips/mach-mtmips/mt76xx.h b/arch/mips/mach-mtmips/mt76xx.h
new file mode 100644
index 0000000000..17473ea8f1
--- /dev/null
+++ b/arch/mips/mach-mtmips/mt76xx.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __MT76XX_H
+#define __MT76XX_H
+
+#define MT76XX_SYSCTL_BASE 0x10000000
+
+#define MT76XX_CHIPID_OFFS 0x00
+#define MT76XX_CHIP_REV_ID_OFFS 0x0c
+#define MT76XX_SYSCFG0_OFFS 0x10
+
+#define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300)
+#define MT76XX_RGCTRL_BASE (MT76XX_SYSCTL_BASE + 0x1000)
+
+#define MT76XX_ROM_STATUS_REG (MT76XX_SYSCTL_BASE + 0x0028)
+#define MT76XX_CLKCFG0_REG (MT76XX_SYSCTL_BASE + 0x002c)
+#define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440)
+
+#define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44)
+#define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48)
+#define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c)
+#define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50)
+
+#ifndef __ASSEMBLY__
+/* Prototypes */
+void ddr_calibrate(void);
+#endif
+
+#endif