summaryrefslogtreecommitdiff
path: root/arch/avr32/cpu/at32ap700x
diff options
context:
space:
mode:
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2017-07-05 16:25:22 +0300
committerTom Rini <trini@konsulko.com>2017-07-06 16:17:19 -0400
commitdaab59ac05d8fd1092e34a4c695ac265ae700141 (patch)
treec9fe90a80281235d0bf3043d1d2e7c218f3ed383 /arch/avr32/cpu/at32ap700x
parent747c4c68c042babb2179b52b60bc78611e3e1183 (diff)
downloadu-boot-daab59ac05d8fd1092e34a4c695ac265ae700141.tar.gz
avr32: Retire AVR32 for good
AVR32 is gone. It's already more than two years for no support in Buildroot, even longer there is no support in GCC (last version is heavily patched 4.2.4). Linux kernel v4.12 got rid of it (and v4.11 didn't build successfully). There is no good point to keep this support in U-Boot either. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'arch/avr32/cpu/at32ap700x')
-rw-r--r--arch/avr32/cpu/at32ap700x/Makefile7
-rw-r--r--arch/avr32/cpu/at32ap700x/clk.c82
-rw-r--r--arch/avr32/cpu/at32ap700x/mmu.c78
-rw-r--r--arch/avr32/cpu/at32ap700x/portmux.c278
-rw-r--r--arch/avr32/cpu/at32ap700x/sm.h204
5 files changed, 0 insertions, 649 deletions
diff --git a/arch/avr32/cpu/at32ap700x/Makefile b/arch/avr32/cpu/at32ap700x/Makefile
deleted file mode 100644
index 06f18963e2..0000000000
--- a/arch/avr32/cpu/at32ap700x/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := portmux.o clk.o mmu.o
diff --git a/arch/avr32/cpu/at32ap700x/clk.c b/arch/avr32/cpu/at32ap700x/clk.c
deleted file mode 100644
index 0fc6088e3e..0000000000
--- a/arch/avr32/cpu/at32ap700x/clk.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2005-2008 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/portmux.h>
-
-#include "sm.h"
-
-void clk_init(void)
-{
- uint32_t cksel;
-
- /* in case of soft resets, disable watchdog */
- sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
- sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
-
-#ifdef CONFIG_PLL
- /* Initialize the PLL */
- sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES)
- | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1)
- | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1)
- | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT)
- | SM_BF(PLLOSC, 0)
- | SM_BIT(PLLEN)));
-
- /* Wait for lock */
- while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
-#endif
-
- /* Set up clocks for the CPU and all peripheral buses */
- cksel = 0;
- if (CONFIG_SYS_CLKDIV_CPU)
- cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1);
- if (CONFIG_SYS_CLKDIV_HSB)
- cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1);
- if (CONFIG_SYS_CLKDIV_PBA)
- cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1);
- if (CONFIG_SYS_CLKDIV_PBB)
- cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1);
- sm_writel(PM_CKSEL, cksel);
-
-#ifdef CONFIG_PLL
- /* Use PLL0 as main clock */
- sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
-
-#ifdef CONFIG_LCD
- /* Set up pixel clock for the LCDC */
- sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN));
-#endif
-#endif
-}
-
-unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
- unsigned long rate, unsigned long parent_rate)
-{
- unsigned long divider;
-
- if (rate == 0 || parent_rate == 0) {
- sm_writel(PM_GCCTRL(id), 0);
- return 0;
- }
-
- divider = (parent_rate + rate / 2) / rate;
- if (divider <= 1) {
- sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
- rate = parent_rate;
- } else {
- divider = min(255UL, divider / 2 - 1);
- sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
- | SM_BF(DIV, divider));
- rate = parent_rate / (2 * (divider + 1));
- }
-
- return rate;
-}
diff --git a/arch/avr32/cpu/at32ap700x/mmu.c b/arch/avr32/cpu/at32ap700x/mmu.c
deleted file mode 100644
index f5e62f27eb..0000000000
--- a/arch/avr32/cpu/at32ap700x/mmu.c
+++ /dev/null
@@ -1,78 +0,0 @@
-#include <common.h>
-#include <asm/arch/mmu.h>
-#include <asm/sysreg.h>
-
-void mmu_init_r(unsigned long dest_addr)
-{
- uintptr_t vmr_table_addr;
-
- /* Round monitor address down to the nearest page boundary */
- dest_addr &= MMU_PAGE_ADDR_MASK;
-
- /* Initialize TLB entry 0 to cover the monitor, and lock it */
- sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
- sysreg_write(TLBELO, dest_addr | MMU_VMR_CACHE_WRBACK);
- sysreg_write(MMUCR, SYSREG_BF(DRP, 0) | SYSREG_BF(DLA, 1)
- | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M));
- __builtin_tlbw();
-
- /*
- * Calculate the address of the VM range table in a PC-relative
- * manner to make sure we hit the SDRAM and not the flash.
- */
- vmr_table_addr = (uintptr_t)&mmu_vmr_table;
- sysreg_write(PTBR, vmr_table_addr);
- printf("VMR table @ 0x%08lx\n", vmr_table_addr);
-
- /* Enable paging */
- sysreg_write(MMUCR, SYSREG_BF(DRP, 1) | SYSREG_BF(DLA, 1)
- | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M) | SYSREG_BIT(E));
-}
-
-int mmu_handle_tlb_miss(void)
-{
- const struct mmu_vm_range *vmr_table;
- const struct mmu_vm_range *vmr;
- unsigned int fault_pgno;
- int first, last;
-
- fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
- vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
-
- /* Do a binary search through the VM ranges */
- first = 0;
- last = CONFIG_SYS_NR_VM_REGIONS;
- while (first < last) {
- unsigned int start;
- int middle;
-
- /* Pick the entry in the middle of the remaining range */
- middle = (first + last) >> 1;
- vmr = &vmr_table[middle];
- start = vmr->virt_pgno;
-
- /* Do the bisection thing */
- if (fault_pgno < start) {
- last = middle;
- } else if (fault_pgno >= (start + vmr->nr_pages)) {
- first = middle + 1;
- } else {
- /* Got it; let's slam it into the TLB */
- uint32_t tlbelo;
-
- tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
- tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
- sysreg_write(TLBELO, tlbelo);
- __builtin_tlbw();
-
- /* Zero means success */
- return 0;
- }
- }
-
- /*
- * Didn't find any matching entries. Return a nonzero value to
- * indicate that this should be treated as a fatal exception.
- */
- return -1;
-}
diff --git a/arch/avr32/cpu/at32ap700x/portmux.c b/arch/avr32/cpu/at32ap700x/portmux.c
deleted file mode 100644
index 58327bac87..0000000000
--- a/arch/avr32/cpu/at32ap700x/portmux.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/chip-features.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/portmux.h>
-
-/*
- * Lots of small functions here. We depend on --gc-sections getting
- * rid of the ones we don't need.
- */
-void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
- unsigned long flags, unsigned long drive_strength)
-{
- unsigned long porte_mask = 0;
-
- if (bus_width > 16)
- portmux_select_peripheral(PORTMUX_PORT_E, 0xffff,
- PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
- if (addr_width > 23)
- porte_mask |= (((1 << (addr_width - 23)) - 1) & 7) << 16;
- if (flags & PORTMUX_EBI_CS(2))
- porte_mask |= 1 << 25;
- if (flags & PORTMUX_EBI_CS(4))
- porte_mask |= 1 << 21;
- if (flags & PORTMUX_EBI_CS(5))
- porte_mask |= 1 << 22;
- if (flags & (PORTMUX_EBI_CF(0) | PORTMUX_EBI_CF(1)))
- porte_mask |= (1 << 19) | (1 << 20) | (1 << 23);
-
- portmux_select_peripheral(PORTMUX_PORT_E, porte_mask,
- PORTMUX_FUNC_A, 0);
-
- if (flags & PORTMUX_EBI_NWAIT)
- portmux_select_peripheral(PORTMUX_PORT_E, 1 << 24,
- PORTMUX_FUNC_A, PORTMUX_PULL_UP);
-}
-
-#ifdef AT32AP700x_CHIP_HAS_MACB
-void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength)
-{
- unsigned long portc_mask;
-
- portc_mask = (1 << 3) /* TXD0 */
- | (1 << 4) /* TXD1 */
- | (1 << 7) /* TXEN */
- | (1 << 8) /* TXCK */
- | (1 << 9) /* RXD0 */
- | (1 << 10) /* RXD1 */
- | (1 << 13) /* RXER */
- | (1 << 15) /* RXDV */
- | (1 << 16) /* MDC */
- | (1 << 17); /* MDIO */
-
- if (flags & PORTMUX_MACB_MII)
- portc_mask |= (1 << 0) /* COL */
- | (1 << 1) /* CRS */
- | (1 << 2) /* TXER */
- | (1 << 5) /* TXD2 */
- | (1 << 6) /* TXD3 */
- | (1 << 11) /* RXD2 */
- | (1 << 12) /* RXD3 */
- | (1 << 14); /* RXCK */
-
- if (flags & PORTMUX_MACB_SPEED)
- portc_mask |= (1 << 18);/* SPD */
-
- /* REVISIT: Some pins are probably pure outputs */
- portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
- PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-}
-
-void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength)
-{
- unsigned long portc_mask = 0;
- unsigned long portd_mask;
-
- portd_mask = (1 << 13) /* TXD0 */
- | (1 << 14) /* TXD1 */
- | (1 << 11) /* TXEN */
- | (1 << 12) /* TXCK */
- | (1 << 10) /* RXD0 */
- | (1 << 6) /* RXD1 */
- | (1 << 5) /* RXER */
- | (1 << 4) /* RXDV */
- | (1 << 3) /* MDC */
- | (1 << 2); /* MDIO */
-
- if (flags & PORTMUX_MACB_MII)
- portc_mask = (1 << 19) /* COL */
- | (1 << 23) /* CRS */
- | (1 << 26) /* TXER */
- | (1 << 27) /* TXD2 */
- | (1 << 28) /* TXD3 */
- | (1 << 29) /* RXD2 */
- | (1 << 30) /* RXD3 */
- | (1 << 24); /* RXCK */
-
- if (flags & PORTMUX_MACB_SPEED)
- portd_mask |= (1 << 15);/* SPD */
-
- /* REVISIT: Some pins are probably pure outputs */
- portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
- PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
- portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
- PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_MMCI
-void portmux_enable_mmci(unsigned int slot, unsigned long flags,
- unsigned long drive_strength)
-{
- unsigned long mask;
- unsigned long portmux_flags = PORTMUX_PULL_UP;
-
- /* First, the common CLK signal. It doesn't need a pull-up */
- portmux_select_peripheral(PORTMUX_PORT_A, 1 << 10,
- PORTMUX_FUNC_A, 0);
-
- if (flags & PORTMUX_MMCI_EXT_PULLUP)
- portmux_flags = 0;
-
- /* Then, the per-slot signals */
- switch (slot) {
- case 0:
- mask = (1 << 11) | (1 << 12); /* CMD and DATA0 */
- if (flags & PORTMUX_MMCI_4BIT)
- /* DATA1..DATA3 */
- mask |= (1 << 13) | (1 << 14) | (1 << 15);
- portmux_select_peripheral(PORTMUX_PORT_A, mask,
- PORTMUX_FUNC_A, portmux_flags);
- break;
- case 1:
- mask = (1 << 6) | (1 << 7); /* CMD and DATA0 */
- if (flags & PORTMUX_MMCI_4BIT)
- /* DATA1..DATA3 */
- mask |= (1 << 8) | (1 << 9) | (1 << 10);
- portmux_select_peripheral(PORTMUX_PORT_B, mask,
- PORTMUX_FUNC_B, portmux_flags);
- break;
- }
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_SPI
-void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength)
-{
- unsigned long pin_mask;
-
- /* MOSI and SCK */
- portmux_select_peripheral(PORTMUX_PORT_A, (1 << 1) | (1 << 2),
- PORTMUX_FUNC_A, 0);
- /* MISO may float */
- portmux_select_peripheral(PORTMUX_PORT_A, 1 << 0,
- PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-
- /* Set up NPCSx as GPIO outputs, initially high */
- pin_mask = (cs_mask & 7) << 3;
- if (cs_mask & (1 << 3))
- pin_mask |= 1 << 20;
-
- portmux_select_gpio(PORTMUX_PORT_A, pin_mask,
- PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-}
-
-void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength)
-{
- /* MOSI and SCK */
- portmux_select_peripheral(PORTMUX_PORT_B, (1 << 1) | (1 << 5),
- PORTMUX_FUNC_B, 0);
- /* MISO may float */
- portmux_select_peripheral(PORTMUX_PORT_B, 1 << 0,
- PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-
- /* Set up NPCSx as GPIO outputs, initially high */
- portmux_select_gpio(PORTMUX_PORT_B, (cs_mask & 7) << 2,
- PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
- portmux_select_gpio(PORTMUX_PORT_A, (cs_mask & 8) << (27 - 3),
- PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_LCDC
-void portmux_enable_lcdc(int pin_config)
-{
- unsigned long portc_mask = 0;
- unsigned long portd_mask = 0;
- unsigned long porte_mask = 0;
-
- switch (pin_config) {
- case 0:
- portc_mask = (1 << 19) /* CC */
- | (1 << 20) /* HSYNC */
- | (1 << 21) /* PCLK */
- | (1 << 22) /* VSYNC */
- | (1 << 23) /* DVAL */
- | (1 << 24) /* MODE */
- | (1 << 25) /* PWR */
- | (1 << 26) /* DATA0 */
- | (1 << 27) /* DATA1 */
- | (1 << 28) /* DATA2 */
- | (1 << 29) /* DATA3 */
- | (1 << 30) /* DATA4 */
- | (1 << 31); /* DATA5 */
-
- portd_mask = (1 << 0) /* DATA6 */
- | (1 << 1) /* DATA7 */
- | (1 << 2) /* DATA8 */
- | (1 << 3) /* DATA9 */
- | (1 << 4) /* DATA10 */
- | (1 << 5) /* DATA11 */
- | (1 << 6) /* DATA12 */
- | (1 << 7) /* DATA13 */
- | (1 << 8) /* DATA14 */
- | (1 << 9) /* DATA15 */
- | (1 << 10) /* DATA16 */
- | (1 << 11) /* DATA17 */
- | (1 << 12) /* DATA18 */
- | (1 << 13) /* DATA19 */
- | (1 << 14) /* DATA20 */
- | (1 << 15) /* DATA21 */
- | (1 << 16) /* DATA22 */
- | (1 << 17); /* DATA23 */
- break;
-
- case 1:
- portc_mask = (1 << 20) /* HSYNC */
- | (1 << 21) /* PCLK */
- | (1 << 22) /* VSYNC */
- | (1 << 25) /* PWR */
- | (1 << 31); /* DATA5 */
-
- portd_mask = (1 << 0) /* DATA6 */
- | (1 << 1) /* DATA7 */
- | (1 << 7) /* DATA13 */
- | (1 << 8) /* DATA14 */
- | (1 << 9) /* DATA15 */
- | (1 << 16) /* DATA22 */
- | (1 << 17); /* DATA23 */
-
- porte_mask = (1 << 0) /* CC */
- | (1 << 1) /* DVAL */
- | (1 << 2) /* MODE */
- | (1 << 3) /* DATA0 */
- | (1 << 4) /* DATA1 */
- | (1 << 5) /* DATA2 */
- | (1 << 6) /* DATA3 */
- | (1 << 7) /* DATA4 */
- | (1 << 8) /* DATA8 */
- | (1 << 9) /* DATA9 */
- | (1 << 10) /* DATA10 */
- | (1 << 11) /* DATA11 */
- | (1 << 12) /* DATA12 */
- | (1 << 13) /* DATA16 */
- | (1 << 14) /* DATA17 */
- | (1 << 15) /* DATA18 */
- | (1 << 16) /* DATA19 */
- | (1 << 17) /* DATA20 */
- | (1 << 18); /* DATA21 */
- break;
- }
-
- /* REVISIT: Some pins are probably pure outputs */
- portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
- PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
- portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
- PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
- portmux_select_peripheral(PORTMUX_PORT_E, porte_mask,
- PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-}
-#endif
diff --git a/arch/avr32/cpu/at32ap700x/sm.h b/arch/avr32/cpu/at32ap700x/sm.h
deleted file mode 100644
index 9a3804efe4..0000000000
--- a/arch/avr32/cpu/at32ap700x/sm.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Register definitions for System Manager
- */
-#ifndef __CPU_AT32AP_SM_H__
-#define __CPU_AT32AP_SM_H__
-
-/* SM register offsets */
-#define SM_PM_MCCTRL 0x0000
-#define SM_PM_CKSEL 0x0004
-#define SM_PM_CPU_MASK 0x0008
-#define SM_PM_HSB_MASK 0x000c
-#define SM_PM_PBA_MASK 0x0010
-#define SM_PM_PBB_MASK 0x0014
-#define SM_PM_PLL0 0x0020
-#define SM_PM_PLL1 0x0024
-#define SM_PM_VCTRL 0x0030
-#define SM_PM_VMREF 0x0034
-#define SM_PM_VMV 0x0038
-#define SM_PM_IER 0x0040
-#define SM_PM_IDR 0x0044
-#define SM_PM_IMR 0x0048
-#define SM_PM_ISR 0x004c
-#define SM_PM_ICR 0x0050
-#define SM_PM_GCCTRL(x) (0x0060 + 4 * x)
-#define SM_RTC_CTRL 0x0080
-#define SM_RTC_VAL 0x0084
-#define SM_RTC_TOP 0x0088
-#define SM_RTC_IER 0x0090
-#define SM_RTC_IDR 0x0094
-#define SM_RTC_IMR 0x0098
-#define SM_RTC_ISR 0x009c
-#define SM_RTC_ICR 0x00a0
-#define SM_WDT_CTRL 0x00b0
-#define SM_WDT_CLR 0x00b4
-#define SM_WDT_EXT 0x00b8
-#define SM_RC_RCAUSE 0x00c0
-#define SM_EIM_IER 0x0100
-#define SM_EIM_IDR 0x0104
-#define SM_EIM_IMR 0x0108
-#define SM_EIM_ISR 0x010c
-#define SM_EIM_ICR 0x0110
-#define SM_EIM_MODE 0x0114
-#define SM_EIM_EDGE 0x0118
-#define SM_EIM_LEVEL 0x011c
-#define SM_EIM_TEST 0x0120
-#define SM_EIM_NMIC 0x0124
-
-/* Bitfields in PM_CKSEL */
-#define SM_CPUSEL_OFFSET 0
-#define SM_CPUSEL_SIZE 3
-#define SM_CPUDIV_OFFSET 7
-#define SM_CPUDIV_SIZE 1
-#define SM_HSBSEL_OFFSET 8
-#define SM_HSBSEL_SIZE 3
-#define SM_HSBDIV_OFFSET 15
-#define SM_HSBDIV_SIZE 1
-#define SM_PBASEL_OFFSET 16
-#define SM_PBASEL_SIZE 3
-#define SM_PBADIV_OFFSET 23
-#define SM_PBADIV_SIZE 1
-#define SM_PBBSEL_OFFSET 24
-#define SM_PBBSEL_SIZE 3
-#define SM_PBBDIV_OFFSET 31
-#define SM_PBBDIV_SIZE 1
-
-/* Bitfields in PM_PLL0 */
-#define SM_PLLEN_OFFSET 0
-#define SM_PLLEN_SIZE 1
-#define SM_PLLOSC_OFFSET 1
-#define SM_PLLOSC_SIZE 1
-#define SM_PLLOPT_OFFSET 2
-#define SM_PLLOPT_SIZE 3
-#define SM_PLLDIV_OFFSET 8
-#define SM_PLLDIV_SIZE 8
-#define SM_PLLMUL_OFFSET 16
-#define SM_PLLMUL_SIZE 8
-#define SM_PLLCOUNT_OFFSET 24
-#define SM_PLLCOUNT_SIZE 6
-#define SM_PLLTEST_OFFSET 31
-#define SM_PLLTEST_SIZE 1
-
-/* Bitfields in PM_VCTRL */
-#define SM_VAUTO_OFFSET 0
-#define SM_VAUTO_SIZE 1
-#define SM_PM_VCTRL_VAL_OFFSET 8
-#define SM_PM_VCTRL_VAL_SIZE 7
-
-/* Bitfields in PM_VMREF */
-#define SM_REFSEL_OFFSET 0
-#define SM_REFSEL_SIZE 4
-
-/* Bitfields in PM_VMV */
-#define SM_PM_VMV_VAL_OFFSET 0
-#define SM_PM_VMV_VAL_SIZE 8
-
-/* Bitfields in PM_ICR */
-#define SM_LOCK0_OFFSET 0
-#define SM_LOCK0_SIZE 1
-#define SM_LOCK1_OFFSET 1
-#define SM_LOCK1_SIZE 1
-#define SM_WAKE_OFFSET 2
-#define SM_WAKE_SIZE 1
-#define SM_VOK_OFFSET 3
-#define SM_VOK_SIZE 1
-#define SM_VMRDY_OFFSET 4
-#define SM_VMRDY_SIZE 1
-#define SM_CKRDY_OFFSET 5
-#define SM_CKRDY_SIZE 1
-
-/* Bitfields in PM_GCCTRL */
-#define SM_OSCSEL_OFFSET 0
-#define SM_OSCSEL_SIZE 1
-#define SM_PLLSEL_OFFSET 1
-#define SM_PLLSEL_SIZE 1
-#define SM_CEN_OFFSET 2
-#define SM_CEN_SIZE 1
-#define SM_CPC_OFFSET 3
-#define SM_CPC_SIZE 1
-#define SM_DIVEN_OFFSET 4
-#define SM_DIVEN_SIZE 1
-#define SM_DIV_OFFSET 8
-#define SM_DIV_SIZE 8
-
-/* Bitfields in RTC_CTRL */
-#define SM_PCLR_OFFSET 1
-#define SM_PCLR_SIZE 1
-#define SM_TOPEN_OFFSET 2
-#define SM_TOPEN_SIZE 1
-#define SM_CLKEN_OFFSET 3
-#define SM_CLKEN_SIZE 1
-#define SM_PSEL_OFFSET 8
-#define SM_PSEL_SIZE 16
-
-/* Bitfields in RTC_VAL */
-#define SM_RTC_VAL_VAL_OFFSET 0
-#define SM_RTC_VAL_VAL_SIZE 31
-
-/* Bitfields in RTC_TOP */
-#define SM_RTC_TOP_VAL_OFFSET 0
-#define SM_RTC_TOP_VAL_SIZE 32
-
-/* Bitfields in RTC_ICR */
-#define SM_TOPI_OFFSET 0
-#define SM_TOPI_SIZE 1
-
-/* Bitfields in WDT_CTRL */
-#define SM_KEY_OFFSET 24
-#define SM_KEY_SIZE 8
-
-/* Bitfields in RC_RCAUSE */
-#define SM_POR_OFFSET 0
-#define SM_POR_SIZE 1
-#define SM_BOD_OFFSET 1
-#define SM_BOD_SIZE 1
-#define SM_EXT_OFFSET 2
-#define SM_EXT_SIZE 1
-#define SM_WDT_OFFSET 3
-#define SM_WDT_SIZE 1
-#define SM_NTAE_OFFSET 4
-#define SM_NTAE_SIZE 1
-#define SM_SERP_OFFSET 5
-#define SM_SERP_SIZE 1
-
-/* Bitfields in EIM_EDGE */
-#define SM_INT0_OFFSET 0
-#define SM_INT0_SIZE 1
-#define SM_INT1_OFFSET 1
-#define SM_INT1_SIZE 1
-#define SM_INT2_OFFSET 2
-#define SM_INT2_SIZE 1
-#define SM_INT3_OFFSET 3
-#define SM_INT3_SIZE 1
-
-/* Bitfields in EIM_LEVEL */
-
-/* Bitfields in EIM_TEST */
-#define SM_TESTEN_OFFSET 31
-#define SM_TESTEN_SIZE 1
-
-/* Bitfields in EIM_NMIC */
-#define SM_EN_OFFSET 0
-#define SM_EN_SIZE 1
-
-/* Bit manipulation macros */
-#define SM_BIT(name) \
- (1 << SM_##name##_OFFSET)
-#define SM_BF(name,value) \
- (((value) & ((1 << SM_##name##_SIZE) - 1)) \
- << SM_##name##_OFFSET)
-#define SM_BFEXT(name,value) \
- (((value) >> SM_##name##_OFFSET) \
- & ((1 << SM_##name##_SIZE) - 1))
-#define SM_BFINS(name,value,old) \
- (((old) & ~(((1 << SM_##name##_SIZE) - 1) \
- << SM_##name##_OFFSET)) \
- | SM_BF(name,value))
-
-/* Register access macros */
-#define sm_readl(reg) \
- readl((void *)ATMEL_BASE_SM + SM_##reg)
-#define sm_writel(reg,value) \
- writel((value), (void *)ATMEL_BASE_SM + SM_##reg)
-
-#endif /* __CPU_AT32AP_SM_H__ */
View Lorry Controller Status