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| author | Andre Przywara <andre.przywara@arm.com> | 2019-07-15 02:27:08 +0100 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:13:04 +0530 |
| commit | 7656d3982a39127f38d5be4ab4e3f61500739ba7 (patch) | |
| tree | c4cd5dbcaa329c342d0812e31716b5a59fbf037a /arch/arm/mach-sunxi/Kconfig | |
| parent | 75a8a641f313f019c406433856a6793def53dc4d (diff) | |
| download | u-boot-7656d3982a39127f38d5be4ab4e3f61500739ba7.tar.gz | |
sunxi: H6: Add DDR3-1333 timings
Add a routine to program the timing parameters for DDR3-1333 DRAM chips
connected to the H6 DRAM controller.
The values were gathered from doing back-calculations from a register
dump, trying to match them up with the official JEDEC DDDR3 spec.
If in doubt, the register dump values were taken for now, but the JEDEC
recommendation were added as a comment.
Many thanks to Jernej for contributing fixes!
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/mach-sunxi/Kconfig')
| -rw-r--r-- | arch/arm/mach-sunxi/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d588936850..d4e7d89e9e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -378,6 +378,14 @@ config SUNXI_DRAM_H6_LPDDR3 This option is the LPDDR3 timing used by the stock boot0 by Allwinner. +config SUNXI_DRAM_H6_DDR3_1333 + bool "DDR3-1333 boot0 timings on the H6 DRAM controller" + select SUNXI_DRAM_DDR3 + depends on DRAM_SUN50I_H6 + ---help--- + This option is the DDR3 timing used by the boot0 on H6 TV boxes + which use a DDR3-1333 timing. + config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 |