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authorMarek Vasut <marex@denx.de>2018-08-13 18:32:38 +0200
committerMarek Vasut <marex@denx.de>2018-08-13 22:35:17 +0200
commit8145c1c299e6646aa5b68e248fbd8090cd425fba (patch)
treece73f4cdd86479ecb35049d1cf31486c92c6a7c4 /arch/arm/mach-socfpga
parentc29508045f41c0cf110af11ed9340bcc42974e08 (diff)
downloadu-boot-8145c1c299e6646aa5b68e248fbd8090cd425fba.tar.gz
ARM: socfpga: Enable DM reset framework on A10
Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r--arch/arm/mach-socfpga/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 5c1df2cf1f..368f217fc6 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10
bool
select ALTERA_SDRAM
select SPL_BOARD_INIT if SPL
+ select DM_RESET
+ select SPL_DM_RESET if SPL
config TARGET_SOCFPGA_CYCLONE5
bool