diff options
author | Ley Foon Tan <ley.foon.tan@intel.com> | 2018-05-18 22:05:22 +0800 |
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committer | Marek Vasut <marex@denx.de> | 2018-05-18 10:30:47 +0200 |
commit | 508791a035ea8e2698c52e1547f77048c49c4391 (patch) | |
tree | bc3356cea50334f53397a7584fcdf36eb5ca8a74 /arch/arm/mach-socfpga/clock_manager.c | |
parent | 641f7470b66ad513c21ffd8113cca5eca09d1df5 (diff) | |
download | u-boot-508791a035ea8e2698c52e1547f77048c49c4391.tar.gz |
arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC
Add Clock Manager driver support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/clock_manager.c')
-rw-r--r-- | arch/arm/mach-socfpga/clock_manager.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index bc2c0f8854..59ede59b59 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -20,7 +20,7 @@ void cm_wait_for_lock(u32 mask) do { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else inter_val = readl(&clock_manager_base->stat) & mask; #endif /* Wait for stable lock */ @@ -51,7 +51,7 @@ int set_cpu_clk_info(void) #if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else gd->bd->bi_ddr_freq = 0; #endif |