diff options
| author | Wolfgang Denk <wd@denx.de> | 2011-12-07 09:09:58 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-12-07 09:09:58 +0100 |
| commit | c786f54b9ace5d7b20a0404a7deb1bae683cd4e8 (patch) | |
| tree | 8c612b0abb45c0b1bb1ca39df97620a0ab026797 /arch/arm/include/asm | |
| parent | 99dee4b2ef570f289e2b1f105df0fdb8ad57ebd1 (diff) | |
| parent | 15422043c4a213dc5d7d59a337be1ab34c9b2e7f (diff) | |
| download | u-boot-c786f54b9ace5d7b20a0404a7deb1bae683cd4e8.tar.gz | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
davinci: Remove unwanted memsize.c from hawkboard's nand spl build
devkit8000: Move CONFIG_SYS_TEXT_BASE out of bss
da850evm: pass board revision info to kernel
arch/arm/include/asm/arch-omap5/clocks.h: Fix GCC 4.2 warnings
arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warnings
arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warnings
MX35: flea3: changes due to hardware revision B
MX: serial_mxc: cleanup removing nasty #ifdef
M28: Fix OB1 bug in GPIO driver
MXS: Add static annotations to dma driver
apbh_dma: return error value on timeout
Efika: Configure additional regulators for HDMI output
mx5: Correct a warning in clock.c
MC13892: Add REGMODE0 bits definitions
mx51evk: Configure the pins as GPIOs prior to using gpio_get_value
mx53smd: Configure the pins as GPIOs prior to using gpio_get_value
mx53evk: Configure the pins as GPIOs prior to using gpio_get_value
mx53ard: Configure the pins as GPIOs prior to using gpio_get_value
mx53loco: Configure the pins as GPIOs prior to using gpio_get_value
OMAP3: Add SPL_BOARD_INIT hook
AM3517 CraneBoard: Add SPL support
AM3517: Add SPL support
OMAP3: Add SPL support to omap3_evm
OMAP3: Add SPL support to Beagleboard
OMAP3 SPL: Add identify_nand_chip function
OMAP3 SPL: Rework memory initalization and devkit8000 support
OMAP3: Suffix all Micron memory timing parts with their speed
OMAP3: Add optimal SDRC autorefresh control values
omap3: mem: Add MCFG helper macro
OMAP3: Remove get_mem_type prototype
OMAP3: Change mem_ok to clear again after reading back
OMAP3: Add a helper function to set timings in SDRC
OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()
omap3: mem: Comment enable_gpmc_cs_config more
ARM: davici_emac: Fix condition for number of phy detects
arm: printf() is not available in some SPL configurations
arm, davinci: add support for am1808 based enbw_cmc board
arm, davinci: move misc function in arch tree
arm, board/davinci/common/misc.c: Codingstyle cleanup
arm, davinci, da850: add uart1 tx rx pinmux config
arm, davinci: move davinci_rtc struct to hardware.h
arm, davinci: Remove duplication of pinmux configuration code
arm, hawkboard: Use the pinmux configurations defined in the arch tree
arm, da850evm: Use the pinmux configurations defined in the arch tree
arm, da850: Add pinmux configurations to the arch tree
arm, da850evm: Do pinmux configuration for EMAC together with other pinmuxes
arm, hawkboard: Remove obsolete struct pinmux_config i2c_pins
arm, davinci: Move pinmux functions from board to arch tree
arm, arm926ejs: always do cpu critical inits
omap_gpmc: use SOFTECC in SPL if it's enabled
nand_spl_simple: add support for software ECC
AM3517: move AM3517 specific mux defines to generic header
AM35xx: add EMAC support
davinci_emac: hardcode 100Mbps for AM35xx and RMII
davinci_emac: fix for running with dcache enabled
arm926ejs: add noop implementation for dcache ops
davinci_emac: conditionally compile specific PHY support
davinci_emac: use internal addresses in buffer descriptors
davinci_emac: move arch-independent defines to separate header
BeagleBoard: config: Really switch to ttyO2
ARM: davinci_dm6467Tevm: Fix build breakage
ARM: OMAP: Remove STACKSIZE for IRQ and FIQ if unused
ARM: OMAP3: Remove unused define SDRC_R_C_B
ARM: OMAP3: Remove unused define CONFIG_OMAP3430
omap4: fix IO setting
omap4+: streamline CONFIG_SYS_TEXT_BASE and other SDRAM addresses
omap4460: add ES1.1 identification
omap4: emif: fix error in driver
omap: remove I2C from SPL
omap4460: fix TPS initialization
omap: fix cache line size for omap3/omap4 boards
omap4: ttyO2 instead of ttyS2 in default bootargs
omap: Improve PLL parameter calculation tool
start.S: remove omap3 specific code from start.S
armv7: setup vector
armv7: include armv7/cpu.c in SPL build
armv7: disable L2 cache in cleanup_before_linux()
arm, arm926ejs: Fix clear bss loop for zero length bss
PXA: Move colibri_pxa270 to board/toradex/
PXA: Flip colibri_pxa27x to pxa-common.h
PXA: Introduce common configuration header for PXA
PXA: Rename pxa_dram_init to pxa2xx_dram_init
PXA: Squash extern pxa_dram_init()
PXA: Export cpu_is_ and pxa_dram_init functions
PXA: Cleanup Colibri PXA270
PXA: Replace timer driver
PXA: Add cpuinfo display for PXA2xx
PXA: Separate PXA2xx CPU init
PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X
PXA: Unify vpac270 environment size
PXA: Enable command line editing for vpac270
PXA: Adapt Voipac PXA270 to OneNAND SPL
PXA: Drop Voipac PXA270 OneNAND IPL
PXA: Fixup PXA25x boards after start.S update
PXA: Re-add the Dcache locking as RAM for pxa250
PXA: Rework start.S to be closer to other ARMs
PXA: Drop XM250 board
PXA: Drop PLEB2 board
PXA: Drop CRADLE board
PXA: Drop CERF250 board
Fix regression in SMDK6400
nand: Add common functions to linux/mtd/nand.h
Ethernut 5 board support
net: Armada100: Fix compilation warnings
ARM: remove duplicated code for LaCie boards
ARM: add support for LaCie 2Big Network v2
mvsata: fix ide_preinit for missing disks
netspace_v2: Read Ethernet MAC address from EEPROM
omap3evm: Add support for EFI partitions
part_efi: Fix compile errors
Diffstat (limited to 'arch/arm/include/asm')
20 files changed, 390 insertions, 413 deletions
diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h index ea52888ff4..8a17de9054 100644 --- a/arch/arm/include/asm/arch-davinci/emac_defs.h +++ b/arch/arm/include/asm/arch-davinci/emac_defs.h @@ -84,295 +84,6 @@ #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ #endif -/* Ethernet Min/Max packet size */ -#define EMAC_MIN_ETHERNET_PKT_SIZE 60 -#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ - -/* Number of RX packet buffers - * NOTE: Only 1 buffer supported as of now - */ -#define EMAC_MAX_RX_BUFFERS 10 - - -/*********************************************** - ******** Internally used macros *************** - ***********************************************/ - -#define EMAC_CH_TX 1 -#define EMAC_CH_RX 0 - -/* Each descriptor occupies 4 words, lets start RX desc's at 0 and - * reserve space for 64 descriptors max - */ -#define EMAC_RX_DESC_BASE 0x0 -#define EMAC_TX_DESC_BASE 0x1000 - -/* EMAC Teardown value */ -#define EMAC_TEARDOWN_VALUE 0xfffffffc - -/* MII Status Register */ -#define MII_STATUS_REG 1 - -/* Number of statistics registers */ -#define EMAC_NUM_STATS 36 - - -/* EMAC Descriptor */ -typedef volatile struct _emac_desc -{ - u_int32_t next; /* Pointer to next descriptor in chain */ - u_int8_t *buffer; /* Pointer to data buffer */ - u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ - u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ -} emac_desc; - -/* CPPI bit positions */ -#define EMAC_CPPI_SOP_BIT (0x80000000) -#define EMAC_CPPI_EOP_BIT (0x40000000) -#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) -#define EMAC_CPPI_EOQ_BIT (0x10000000) -#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) -#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) - -#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) - -#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) -#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) - -#define EMAC_MAC_ADDR_MATCH (1 << 19) -#define EMAC_MAC_ADDR_IS_VALID (1 << 20) - -#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) -#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) - - -#define MDIO_CONTROL_IDLE (0x80000000) -#define MDIO_CONTROL_ENABLE (0x40000000) -#define MDIO_CONTROL_FAULT_ENABLE (0x40000) -#define MDIO_CONTROL_FAULT (0x80000) -#define MDIO_USERACCESS0_GO (0x80000000) -#define MDIO_USERACCESS0_WRITE_READ (0x0) -#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) -#define MDIO_USERACCESS0_ACK (0x20000000) - -/* Ethernet MAC Registers Structure */ -typedef struct { - dv_reg TXIDVER; - dv_reg TXCONTROL; - dv_reg TXTEARDOWN; - u_int8_t RSVD0[4]; - dv_reg RXIDVER; - dv_reg RXCONTROL; - dv_reg RXTEARDOWN; - u_int8_t RSVD1[100]; - dv_reg TXINTSTATRAW; - dv_reg TXINTSTATMASKED; - dv_reg TXINTMASKSET; - dv_reg TXINTMASKCLEAR; - dv_reg MACINVECTOR; - u_int8_t RSVD2[12]; - dv_reg RXINTSTATRAW; - dv_reg RXINTSTATMASKED; - dv_reg RXINTMASKSET; - dv_reg RXINTMASKCLEAR; - dv_reg MACINTSTATRAW; - dv_reg MACINTSTATMASKED; - dv_reg MACINTMASKSET; - dv_reg MACINTMASKCLEAR; - u_int8_t RSVD3[64]; - dv_reg RXMBPENABLE; - dv_reg RXUNICASTSET; - dv_reg RXUNICASTCLEAR; - dv_reg RXMAXLEN; - dv_reg RXBUFFEROFFSET; - dv_reg RXFILTERLOWTHRESH; - u_int8_t RSVD4[8]; - dv_reg RX0FLOWTHRESH; - dv_reg RX1FLOWTHRESH; - dv_reg RX2FLOWTHRESH; - dv_reg RX3FLOWTHRESH; - dv_reg RX4FLOWTHRESH; - dv_reg RX5FLOWTHRESH; - dv_reg RX6FLOWTHRESH; - dv_reg RX7FLOWTHRESH; - dv_reg RX0FREEBUFFER; - dv_reg RX1FREEBUFFER; - dv_reg RX2FREEBUFFER; - dv_reg RX3FREEBUFFER; - dv_reg RX4FREEBUFFER; - dv_reg RX5FREEBUFFER; - dv_reg RX6FREEBUFFER; - dv_reg RX7FREEBUFFER; - dv_reg MACCONTROL; - dv_reg MACSTATUS; - dv_reg EMCONTROL; - dv_reg FIFOCONTROL; - dv_reg MACCONFIG; - dv_reg SOFTRESET; - u_int8_t RSVD5[88]; - dv_reg MACSRCADDRLO; - dv_reg MACSRCADDRHI; - dv_reg MACHASH1; - dv_reg MACHASH2; - dv_reg BOFFTEST; - dv_reg TPACETEST; - dv_reg RXPAUSE; - dv_reg TXPAUSE; - u_int8_t RSVD6[16]; - dv_reg RXGOODFRAMES; - dv_reg RXBCASTFRAMES; - dv_reg RXMCASTFRAMES; - dv_reg RXPAUSEFRAMES; - dv_reg RXCRCERRORS; - dv_reg RXALIGNCODEERRORS; - dv_reg RXOVERSIZED; - dv_reg RXJABBER; - dv_reg RXUNDERSIZED; - dv_reg RXFRAGMENTS; - dv_reg RXFILTERED; - dv_reg RXQOSFILTERED; - dv_reg RXOCTETS; - dv_reg TXGOODFRAMES; - dv_reg TXBCASTFRAMES; - dv_reg TXMCASTFRAMES; - dv_reg TXPAUSEFRAMES; - dv_reg TXDEFERRED; - dv_reg TXCOLLISION; - dv_reg TXSINGLECOLL; - dv_reg TXMULTICOLL; - dv_reg TXEXCESSIVECOLL; - dv_reg TXLATECOLL; - dv_reg TXUNDERRUN; - dv_reg TXCARRIERSENSE; - dv_reg TXOCTETS; - dv_reg FRAME64; - dv_reg FRAME65T127; - dv_reg FRAME128T255; - dv_reg FRAME256T511; - dv_reg FRAME512T1023; - dv_reg FRAME1024TUP; - dv_reg NETOCTETS; - dv_reg RXSOFOVERRUNS; - dv_reg RXMOFOVERRUNS; - dv_reg RXDMAOVERRUNS; - u_int8_t RSVD7[624]; - dv_reg MACADDRLO; - dv_reg MACADDRHI; - dv_reg MACINDEX; - u_int8_t RSVD8[244]; - dv_reg TX0HDP; - dv_reg TX1HDP; - dv_reg TX2HDP; - dv_reg TX3HDP; - dv_reg TX4HDP; - dv_reg TX5HDP; - dv_reg TX6HDP; - dv_reg TX7HDP; - dv_reg RX0HDP; - dv_reg RX1HDP; - dv_reg RX2HDP; - dv_reg RX3HDP; - dv_reg RX4HDP; - dv_reg RX5HDP; - dv_reg RX6HDP; - dv_reg RX7HDP; - dv_reg TX0CP; - dv_reg TX1CP; - dv_reg TX2CP; - dv_reg TX3CP; - dv_reg TX4CP; - dv_reg TX5CP; - dv_reg TX6CP; - dv_reg TX7CP; - dv_reg RX0CP; - dv_reg RX1CP; - dv_reg RX2CP; - dv_reg RX3CP; - dv_reg RX4CP; - dv_reg RX5CP; - dv_reg RX6CP; - dv_reg RX7CP; -} emac_regs; - -/* EMAC Wrapper Registers Structure */ -typedef struct { -#ifdef DAVINCI_EMAC_VERSION2 - dv_reg idver; - dv_reg softrst; - dv_reg emctrl; - dv_reg c0rxthreshen; - dv_reg c0rxen; - dv_reg c0txen; - dv_reg c0miscen; - dv_reg c1rxthreshen; - dv_reg c1rxen; - dv_reg c1txen; - dv_reg c1miscen; - dv_reg c2rxthreshen; - dv_reg c2rxen; - dv_reg c2txen; - dv_reg c2miscen; - dv_reg c0rxthreshstat; - dv_reg c0rxstat; - dv_reg c0txstat; - dv_reg c0miscstat; - dv_reg c1rxthreshstat; - dv_reg c1rxstat; - dv_reg c1txstat; - dv_reg c1miscstat; - dv_reg c2rxthreshstat; - dv_reg c2rxstat; - dv_reg c2txstat; - dv_reg c2miscstat; - dv_reg c0rximax; - dv_reg c0tximax; - dv_reg c1rximax; - dv_reg c1tximax; - dv_reg c2rximax; - dv_reg c2tximax; -#else - u_int8_t RSVD0[4100]; - dv_reg EWCTL; - dv_reg EWINTTCNT; -#endif -} ewrap_regs; - -/* EMAC MDIO Registers Structure */ -typedef struct { - dv_reg VERSION; - dv_reg CONTROL; - dv_reg ALIVE; - dv_reg LINK; - dv_reg LINKINTRAW; - dv_reg LINKINTMASKED; - u_int8_t RSVD0[8]; - dv_reg USERINTRAW; - dv_reg USERINTMASKED; - dv_reg USERINTMASKSET; - dv_reg USERINTMASKCLEAR; - u_int8_t RSVD1[80]; - dv_reg USERACCESS0; - dv_reg USERPHYSEL0; - dv_reg USERACCESS1; - dv_reg USERPHYSEL1; -} mdio_regs; - -int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); -int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); - -typedef struct -{ - char name[64]; - int (*init)(int phy_addr); - int (*is_phy_connected)(int phy_addr); - int (*get_link_speed)(int phy_addr); - int (*auto_negotiate)(int phy_addr); -} phy_t; - #define PHY_KSZ8873 (0x00221450) int ksz8873_is_phy_connected(int phy_addr); int ksz8873_get_link_speed(int phy_addr); diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 3e9a3b6de2..dd89e84413 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -480,6 +480,8 @@ struct davinci_syscfg_regs { #define davinci_syscfg_regs \ ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE) +#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) + /* Emulation suspend bits */ #define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) #define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) @@ -586,4 +588,43 @@ static inline int get_async3_src(void) #include <asm/arch/syscfg_defs.h> #include <asm/arch/timer_defs.h> #endif + +struct davinci_rtc { + dv_reg second; + dv_reg minutes; + dv_reg hours; + dv_reg day; + dv_reg month; /* 0x10 */ + dv_reg year; + dv_reg dotw; + dv_reg resv1; + dv_reg alarmsecond; /* 0x20 */ + dv_reg alarmminute; + dv_reg alarmhour; + dv_reg alarmday; + dv_reg alarmmonth; /* 0x30 */ + dv_reg alarmyear; + dv_reg resv2[2]; + dv_reg ctrl; /* 0x40 */ + dv_reg status; + dv_reg irq; + dv_reg complsb; + dv_reg compmsb; /* 0x50 */ + dv_reg osc; + dv_reg resv3[2]; + dv_reg scratch0; /* 0x60 */ + dv_reg scratch1; + dv_reg scratch2; + dv_reg kick0r; + dv_reg kick1r; /* 0x70 */ +}; + +#define RTC_STATE_BUSY 0x01 +#define RTC_STATE_RUN 0x02 + +#define RTC_KICK0R_WE 0x130be783 +#define RTC_KICK1R_WE 0xe0f1a495 + +#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h new file mode 100644 index 0000000000..07aceaab03 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -0,0 +1,51 @@ +/* + * Pinmux configurations for the DAxxx SoCs + * + * Copyright (C) 2011 OMICRON electronics GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_PINMUX_DEFS_H +#define __ASM_ARCH_PINMUX_DEFS_H + +#include <asm/arch/davinci_misc.h> + +/* SPI pin muxer settings */ +extern const struct pinmux_config spi1_pins_base[3]; +extern const struct pinmux_config spi1_pins_scs0[1]; + +/* UART pin muxer settings */ +extern const struct pinmux_config uart1_pins_txrx[2]; +extern const struct pinmux_config uart2_pins_txrx[2]; +extern const struct pinmux_config uart2_pins_rtscts[2]; + +/* EMAC pin muxer settings*/ +extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_mii[15]; +extern const struct pinmux_config emac_pins_mdio[2]; + +/* I2C pin muxer settings */ +extern const struct pinmux_config i2c0_pins[2]; +extern const struct pinmux_config i2c1_pins[2]; + +/* EMIFA pin muxer settings */ +extern const struct pinmux_config emifa_pins_cs2[1]; +extern const struct pinmux_config emifa_pins_cs3[1]; +extern const struct pinmux_config emifa_pins_cs4[1]; +extern const struct pinmux_config emifa_pins_nand[12]; +extern const struct pinmux_config emifa_pins_nor[43]; + +#endif diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index eece138b45..7f9449b2d0 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -180,8 +180,8 @@ struct aips_regs { #define IMX_I2C3_BASE (0x43F84000) #define IMX_CAN1_BASE (0x43F88000) #define IMX_CAN2_BASE (0x43F8C000) -#define IMX_UART1_BASE (0x43F90000) -#define IMX_UART2_BASE (0x43F94000) +#define UART1_BASE (0x43F90000) +#define UART2_BASE (0x43F94000) #define IMX_I2C2_BASE (0x43F98000) #define IMX_OWIRE_BASE (0x43F9C000) #define IMX_CSPI1_BASE (0x43FA4000) @@ -197,15 +197,15 @@ struct aips_regs { /* SPBA */ #define IMX_SPBA_BASE (0x50000000) #define IMX_CSPI3_BASE (0x50004000) -#define IMX_UART4_BASE (0x50008000) -#define IMX_UART3_BASE (0x5000C000) +#define UART4_BASE (0x50008000) +#define UART3_BASE (0x5000C000) #define IMX_CSPI2_BASE (0x50010000) #define IMX_SSI2_BASE (0x50014000) #define IMX_ESAI_BASE (0x50018000) #define IMX_ATA_DMA_BASE (0x50020000) #define IMX_SIM1_BASE (0x50024000) #define IMX_SIM2_BASE (0x50028000) -#define IMX_UART5_BASE (0x5002C000) +#define UART5_BASE (0x5002C000) #define IMX_TSC_BASE (0x50030000) #define IMX_SSI1_BASE (0x50034000) #define IMX_FEC_BASE (0x50038000) diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 83ab216665..ced5b2a38c 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -224,10 +224,10 @@ struct fuse_bank0_regs { #define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) +#define UART1_BASE (0x0a000 + IMX_IO_BASE) +#define UART2_BASE (0x0b000 + IMX_IO_BASE) +#define UART3_BASE (0x0c000 + IMX_IO_BASE) +#define UART4_BASE (0x0d000 + IMX_IO_BASE) #define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) diff --git a/arch/arm/include/asm/arch-mx28/dma.h b/arch/arm/include/asm/arch-mx28/dma.h index 7061e7c2fe..52747e2fbf 100644 --- a/arch/arm/include/asm/arch-mx28/dma.h +++ b/arch/arm/include/asm/arch-mx28/dma.h @@ -135,36 +135,11 @@ struct mxs_dma_chan { struct list_head done; }; -/* Hardware management ops */ -int mxs_dma_enable(int channel); -int mxs_dma_disable(int channel); -int mxs_dma_reset(int channel); -int mxs_dma_freeze(int channel); -int mxs_dma_unfreeze(int channel); -int mxs_dma_read_semaphore(int channel); -int mxs_dma_enable_irq(int channel, int enable); -int mxs_dma_irq_is_pending(int channel); -int mxs_dma_ack_irq(int channel); - -/* Channel management ops */ -int mxs_dma_request(int channel); -int mxs_dma_release(int channel); - -/* Descriptor management ops */ struct mxs_dma_desc *mxs_dma_desc_alloc(void); void mxs_dma_desc_free(struct mxs_dma_desc *); - -unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc); -int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc); - int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); -int mxs_dma_get_finished(int channel, struct list_head *head); -int mxs_dma_finish(int channel, struct list_head *head); - -int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan); int mxs_dma_go(int chan); - int mxs_dma_init(void); #endif /* __DMA_H__ */ diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 0147920e4b..6a517ddd93 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -600,6 +600,12 @@ struct esdc_regs { #define WEIM_ESDCFG1 0xB800100C #define WEIM_ESDMISC 0xB8001010 +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 +#define UART3_BASE 0x5000C000 +#define UART4_BASE 0x43FB0000 +#define UART5_BASE 0x43FB4000 + #define ESDCTL_SDE (1 << 31) #define ESDCTL_CMD_RW (0 << 28) #define ESDCTL_CMD_PRECHARGE (1 << 28) diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index 25c324eb36..df74508a93 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -42,8 +42,8 @@ #define I2C_BASE_ADDR 0x43F80000 #define I2C3_BASE_ADDR 0x43F84000 #define ATA_BASE_ADDR 0x43F8C000 -#define UART1_BASE_ADDR 0x43F90000 -#define UART2_BASE_ADDR 0x43F94000 +#define UART1_BASE 0x43F90000 +#define UART2_BASE 0x43F94000 #define I2C2_BASE_ADDR 0x43F98000 #define CSPI1_BASE_ADDR 0x43FA4000 #define IOMUXC_BASE_ADDR 0x43FAC000 @@ -52,7 +52,7 @@ * SPBA */ #define SPBA_BASE_ADDR 0x50000000 -#define UART3_BASE_ADDR 0x5000C000 +#define UART3_BASE 0x5000C000 #define CSPI2_BASE_ADDR 0x50010000 #define ATA_DMA_BASE_ADDR 0x50020000 #define FEC_BASE_ADDR 0x50038000 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d069209b58..0ee88d25b7 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -54,7 +54,7 @@ */ #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) -#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) @@ -83,8 +83,8 @@ #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) -#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) -#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h index 81942a8063..bbaf1bc97b 100644 --- a/arch/arm/include/asm/arch-omap3/am35x_def.h +++ b/arch/arm/include/asm/arch-omap3/am35x_def.h @@ -32,6 +32,9 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ +/* IP_SW_RESET bits */ +#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ + /* General register mappings of system control module */ #define AM35X_SCM_GEN_BASE 0x48002270 struct am35x_scm_general { diff --git a/arch/arm/include/asm/arch-omap3/emac_defs.h b/arch/arm/include/asm/arch-omap3/emac_defs.h new file mode 100644 index 0000000000..8506c555d5 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/emac_defs.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + * + */ + +#ifndef _AM3517_EMAC_H_ +#define _AM3517_EMAC_H_ + +#define EMAC_BASE_ADDR 0x5C010000 +#define EMAC_WRAPPER_BASE_ADDR 0x5C000000 +#define EMAC_WRAPPER_RAM_ADDR 0x5C020000 +#define EMAC_MDIO_BASE_ADDR 0x5C030000 +#define EMAC_HW_RAM_ADDR 0x01E20000 + +#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */ +#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */ + +/* SOFTRESET macro definition interferes with emac_regs structure definition */ +#undef SOFTRESET + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#define DAVINCI_EMAC_VERSION2 + +#endif /* _AM3517_EMAC_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index db6a696f49..5fd02d4dfc 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -39,10 +39,26 @@ enum { #define EARLY_INIT 1 +/* + * For a full explanation of these registers and values please see + * the Technical Reference Manual (TRM) for any of the processors in + * this family. + */ + /* Slower full frequency range default timings for x32 operation*/ #define SDRC_SHARING 0x00000100 #define SDRC_MR_0_SDR 0x00000031 +/* + * SDRC autorefresh control values. This register consists of autorefresh + * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The + * counter is a result of ( tREFI / tCK ) - 50. + */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + #define DLL_OFFSET 0 #define DLL_WRITEDDRCLKX2DIS 1 #define DLL_ENADLL 1 @@ -86,6 +102,53 @@ enum { ACTIM_CTRLB_TXP(b) | \ ACTIM_CTRLB_TXSR(d) +/* + * Values used in the MCFG register. Only values we use today + * are defined and the rest can be found in the TRM. Unless otherwise + * noted all fields are one bit. + */ +#define V_MCFG_RAMTYPE_DDR (0x1) +#define V_MCFG_DEEPPD_EN (0x1 << 3) +#define V_MCFG_B32NOT16_32 (0x1 << 4) +#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ +#define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */ +#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) +#define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */ +#define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */ + +/* Macro to construct MCFG */ +#define MCFG(a, b) \ + V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \ + V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \ + V_MCFG_BANKALLOCATION_RBC | \ + V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR + +/* Hynix part of AM/DM37xEVM (200MHz optimized) */ +#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 \ + ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ + HYNIX_TRAS_200, HYNIX_TRP_200, \ + HYNIX_TRCD_200, HYNIX_TRRD_200, \ + HYNIX_TDPL_200, HYNIX_TDAL_200) + +#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 \ + ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ + HYNIX_TXP_200, HYNIX_XSR_200) + +#define HYNIX_RASWIDTH_200 0x3 +#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ @@ -138,32 +201,42 @@ enum { ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ MICRON_TXP_165, MICRON_XSR_165) -#define MICRON_RAMTYPE 0x1 -#define MICRON_DDRTYPE 0x0 -#define MICRON_DEEPPD 0x1 -#define MICRON_B32NOT16 0x1 -#define MICRON_BANKALLOCATION 0x2 -#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) -#define MICRON_ADDRMUXLEGACY 0x1 -#define MICRON_CASWIDTH 0x5 -#define MICRON_RASWIDTH 0x2 -#define MICRON_LOCKSTATUS 0x0 -#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ - (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ - (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ - (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ - (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) - -#define MICRON_ARCV 2030 -#define MICRON_ARE 0x1 -#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) - -#define MICRON_BL 0x2 -#define MICRON_SIL 0x0 -#define MICRON_CASL 0x3 -#define MICRON_WBST 0x0 -#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ - (MICRON_SIL << 3) | (MICRON_BL)) +#define MICRON_RASWIDTH_165 0x2 +#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) + +#define MICRON_BL_165 0x2 +#define MICRON_SIL_165 0x0 +#define MICRON_CASL_165 0x3 +#define MICRON_WBST_165 0x0 +#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ + (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ + (MICRON_BL_165)) + +/* Micron part (200MHz optimized) 5 ns */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 \ + ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ + MICRON_TRAS_200, MICRON_TRP_200, \ + MICRON_TRCD_200, MICRON_TRRD_200, \ + MICRON_TDPL_200, MICRON_TDAL_200) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 \ + ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ + MICRON_TXP_200, MICRON_XSR_200) + +#define MICRON_RASWIDTH_200 0x3 +#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ @@ -191,31 +264,8 @@ enum { ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ NUMONYX_TXP_165, NUMONYX_XSR_165) -#ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 -#endif - -#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG -#define V_RFR_CTRL MICRON_V_RFR_CTRL -#define V_MR MICRON_V_MR -#endif - -#ifdef CONFIG_OMAP3_NUMONYX_DDR -#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 -#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 -#endif - -#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) -#error "Please choose the right DDR type in config header" -#endif - -#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) -#error "Please choose the right DDR type in config header" -#endif +#define NUMONYX_RASWIDTH_165 0x4 +#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) /* * GPMC settings - @@ -259,6 +309,10 @@ enum { #define GPMC_SIZE_32M 0xE #define GPMC_SIZE_16M 0xF +#define GPMC_BASEADDR_MASK 0x3F + +#define GPMC_CS_ENABLE 0x1 + #define SMNAND_GPMC_CONFIG1 0x00000800 #define SMNAND_GPMC_CONFIG2 0x00141400 #define SMNAND_GPMC_CONFIG3 0x00141400 diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 0c01c73165..6daef49e97 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -404,6 +404,47 @@ #define CONTROL_PADCONF_SDRC_CKE0 0x0262 #define CONTROL_PADCONF_SDRC_CKE1 0x0264 +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + #define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 02eb865dc1..2b5e9aeae1 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -153,6 +153,7 @@ struct gpio { #define SRAM_OFFSET2 0x0000F800 #define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ SRAM_OFFSET2) +#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) #define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ #define OMAP3_PUBLIC_SRAM_END 0x40210000 diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 995e7cb57e..e5031d5022 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,9 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr); +void identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, @@ -49,7 +52,6 @@ void set_muxconf_regs(void); u32 get_cpu_family(void); u32 get_cpu_rev(void); u32 get_sku_id(void); -u32 get_mem_type(void); u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index e9942574f2..4d8c89ffbd 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -63,6 +63,8 @@ #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F +#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F +#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index fa99f654bd..d0e6dd68da 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -686,14 +686,14 @@ struct dpll_regs { struct dpll_params { u32 m; u32 n; - u8 m2; - u8 m3; - u8 h11; - u8 h12; - u8 h13; - u8 h14; - u8 h22; - u8 h23; + s8 m2; + s8 m3; + s8 h11; + s8 h12; + s8 h13; + s8 h14; + s8 h22; + s8 h23; }; extern struct omap5_prcm_regs *const prcm; diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 52c79a9e64..8527c68c81 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -109,7 +109,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */ #define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */ #define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */ #define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */ #define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */ @@ -126,7 +126,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */ #define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */ #define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #define DCSR(x) (0x40000000 | ((x) << 2)) @@ -134,7 +134,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ -#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ @@ -438,7 +438,7 @@ typedef void (*ExcpHndlr) (void) ; /* * USB Device Controller */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define UDCCR 0x40600000 /* UDC Control Register */ #define UDCCR_UDE (1 << 0) /* UDC enable */ @@ -797,9 +797,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) #define UDC_BCR_MASK (0x3ff) -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) /******************************************************************************/ /* @@ -870,7 +870,7 @@ typedef void (*ExcpHndlr) (void) ; #define UP2OCR_CPVPE (1<<1) #define UP2OCR_CPVEN (1<<0) -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /******************************************************************************/ /* @@ -923,7 +923,7 @@ typedef void (*ExcpHndlr) (void) ; #define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */ #define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */ #define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */ #define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */ @@ -951,7 +951,7 @@ typedef void (*ExcpHndlr) (void) ; #define OMCR10 0x40A000D8 /* OS Match Control Register 10 */ #define OMCR11 0x40A000DC /* OS Match Control Register 11 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #define OSSR_M4 (1 << 4) /* Match status channel 4 */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ @@ -1052,7 +1052,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_PXA27X) +#if !defined(CONFIG_CPU_PXA27X) #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #endif #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ @@ -1071,7 +1071,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ #define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ #endif @@ -1087,7 +1087,7 @@ typedef void (*ExcpHndlr) (void) ; #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ -#if !defined(CONFIG_PXA27X) +#if !defined(CONFIG_CPU_PXA27X) #define CCCR_L09 (0x1F) #define CCCR_L27 (0x1) #define CCCR_L32 (0x2) @@ -1120,7 +1120,7 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */ #define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */ #define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */ #define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */ @@ -1128,7 +1128,7 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */ #define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */ #define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /* * Interrupt Controller @@ -1140,14 +1140,14 @@ typedef void (*ExcpHndlr) (void) ; #define ICPR 0x40D00010 /* Interrupt Controller Pending Register */ #define ICCR 0x40D00014 /* Interrupt Controller Control Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */ #define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */ #define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */ #define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */ #define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /******************************************************************************/ /* @@ -1188,7 +1188,7 @@ typedef void (*ExcpHndlr) (void) ; #define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ #define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ #define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ #define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ @@ -1198,7 +1198,7 @@ typedef void (*ExcpHndlr) (void) ; #define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ #define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ #define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #ifdef CONFIG_CPU_MONAHANS #define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ @@ -1244,7 +1244,7 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) #define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) #define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) #define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) @@ -2123,7 +2123,7 @@ typedef void (*ExcpHndlr) (void) ; #define LCCR0_PDD_S 12 #define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ @@ -2249,7 +2249,7 @@ typedef void (*ExcpHndlr) (void) ; #define LCSR1_IU6 (1 << 29) #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define LDCMD_SOFINT (1 << 22) #define LDCMD_EOFINT (1 << 21) #endif @@ -2480,7 +2480,7 @@ typedef void (*ExcpHndlr) (void) ; #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ @@ -2494,7 +2494,7 @@ typedef void (*ExcpHndlr) (void) ; #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ /* LCD registers */ #define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ @@ -2628,6 +2628,6 @@ typedef void (*ExcpHndlr) (void) ; #define OSCR4 0x40A00040 /* OS Timer Counter Register */ #define OMCR4 0x40A000C0 /* */ -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ #endif /* _PXA_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h new file mode 100644 index 0000000000..49c6552c57 --- /dev/null +++ b/arch/arm/include/asm/arch-pxa/pxa.h @@ -0,0 +1,29 @@ +/* + * PXA common functions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PXA_H__ +#define __PXA_H__ + +int cpu_is_pxa25x(void); +int cpu_is_pxa27x(void); +void pxa2xx_dram_init(void); + +#endif /* __PXA_H__ */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index f1562ea4ab..1ec651b353 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -94,6 +94,10 @@ void spl_nand_load_image(void); /* MMC SPL functions */ void spl_mmc_load_image(void); +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void); +#endif + /* * silicon revisions. * Moving this to common, so that most of code can be moved to common, @@ -108,6 +112,7 @@ void spl_mmc_load_image(void); #define OMAP4430_ES2_2 0x44300220 #define OMAP4430_ES2_3 0x44300230 #define OMAP4460_ES1_0 0x44600100 +#define OMAP4460_ES1_1 0x44600110 /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 |