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| author | Tom Rini <trini@konsulko.com> | 2020-09-24 08:33:47 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-09-24 08:33:47 -0400 |
| commit | 67ece26d8b5d4bfa4fda8c456261c465d0815d7d (patch) | |
| tree | 58d6f1e224c68b9b7b710f63087cb4468394aba7 /arch/arm/dts | |
| parent | e119de72e3ae3accf831b5541d83d5c2faf031ff (diff) | |
| parent | 4ab3817ff16a154981f9394a2c4a0f8f6a72713b (diff) | |
| download | u-boot-67ece26d8b5d4bfa4fda8c456261c465d0815d7d.tar.gz | |
Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into nextWIP/24Sep2020-next
Xilinx changes for v2021.01
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
bindings:
- Add binding doc for vsc8531
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 33 |
1 files changed, 29 insertions, 4 deletions
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index a8bbb14f6c..aae3c626f5 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -230,16 +230,16 @@ #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; - shunt-resistor = <5000>; /* R440 */ - /* 0.78V @ 32A 1 of 6 Phases*/ + shunt-resistor = <500>; /* R440 */ + /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; - shunt-resistor = <2000>; /* R1186 */ - /* 0.78V @ 18A */ + shunt-resistor = <500>; /* R1702 */ + /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; @@ -554,6 +554,31 @@ reg = <7>; }; }; + i2c-mux@75 { /* u214 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { /* SFP0_IIC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* SFP0 */ + }; + i2c@1 { /* SFP1_IIC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* SFP1 */ + }; + i2c@2 { /* QSFP1_I2C */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* QSFP1 */ + }; + /* 3 - 7 unused */ + }; }; &xilinx_ams { |