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| author | Chen-Yu Tsai <wens@csie.org> | 2020-01-12 23:36:13 +0800 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-01-24 23:06:49 +0530 |
| commit | b5fe523bbc2a09069040ca70123246b251cd7daf (patch) | |
| tree | 9a17c140b8bcac14e30e8e9530e3c34424c249cc /arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | |
| parent | 5692e8f7b44c0794ecfe8de92bc64897518623d0 (diff) | |
| download | u-boot-b5fe523bbc2a09069040ca70123246b251cd7daf.tar.gz | |
sunxi: H3/H5 Sync DT files from upstream Linux kernel as of next-20200108
Sync the device tree files and device tree header files from upstream
Linux kernel, as of 2020-01-08. The commit synced to in the sunxi repo
98d25b0b266d Merge branch 'sunxi/dt-for-5.6' into sunxi/for-next
which is also part of next-20200108.
Changes brought in include:
- cleanup of pinmux node names
- addition of Security ID, MBUS, CSI, crypto engine, video codec,
pmu, and thermal sensor device nodes for both SoCs
- addition of deinterlacing engine device node on H3
- cleanup of RTC device node and addition of its clocks
- various board cleanups and improvements
- removal of pinmux node for GPIO lines
- cpufreq / DVFS
- HDMI output
- UART-based Bluetooth
- audio codec
- USB ports
- new boards
Most of the changes don't concern U-boot.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi')
| -rw-r--r-- | arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi new file mode 100644 index 0000000000..22466afd38 --- /dev/null +++ b/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org> + */ + +#include "sunxi-bananapi-m2-plus.dtsi" + +/ { + /* + * Bananapi M2+ v1.2 uses a GPIO line to change the effective + * resistance on the CPU regulator's feedback pin. + */ + reg_vdd_cpux: vdd-cpux { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ + gpios-states = <0x1>; + states = <1100000 0>, <1300000 1>; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; |