diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2019-04-30 16:08:06 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@st.com> | 2019-05-06 09:50:28 +0200 |
| commit | d51761ffc6068595e88cfff2199e8fae039c4afb (patch) | |
| tree | 247b339a72041887dc682fe65a965985e9e5f9ef /arch/arm/dts/stm32f469-disco-u-boot.dtsi | |
| parent | 78d5b61c0ad6ca46764afa9f097d013ad9e9d7f1 (diff) | |
| download | u-boot-d51761ffc6068595e88cfff2199e8fae039c4afb.tar.gz | |
ARM: dts: stm32: Add qspi support for stm32f469-disco board
Add device tree nodes to support qspi for stm32f469-disco board.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/dts/stm32f469-disco-u-boot.dtsi')
| -rw-r--r-- | arch/arm/dts/stm32f469-disco-u-boot.dtsi | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index a980ac46f5..3da308e6a4 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -23,6 +23,7 @@ gpio8 = &gpioi; gpio9 = &gpioj; gpio10 = &gpiok; + spi0 = &qspi; }; soc { @@ -64,6 +65,19 @@ st,sdram-refcount = < 1292 >; }; }; + + qspi: quadspi@A0001000 { + compatible = "st,stm32-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <91>; + spi-max-frequency = <108000000>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; + pinctrl-0 = <&qspi_pins>; + }; }; }; @@ -205,6 +219,18 @@ }; }; + qspi_pins: qspi@0 { + pins { + pinmux = <STM32_PINMUX('F',10, AF9)>, /* CLK */ + <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */ + <STM32_PINMUX('F', 8, AF10)>, /* BK1_IO0 */ + <STM32_PINMUX('F', 9, AF10)>, /* BK1_IO1 */ + <STM32_PINMUX('F', 7, AF9)>, /* BK1_IO2 */ + <STM32_PINMUX('F', 6, AF9)>; /* BK1_IO3 */ + slew-rate = <2>; + }; + }; + usart3_pins_a: usart3@0 { u-boot,dm-pre-reloc; pins1 { @@ -227,3 +253,16 @@ &syscfg { u-boot,dm-pre-reloc; }; + +&qspi { + reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>; + flash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + }; +}; |