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authorTom Rini <trini@konsulko.com>2017-07-11 14:21:50 -0400
committerTom Rini <trini@konsulko.com>2017-07-11 14:21:50 -0400
commitd43ef73bf26614af9b01fd57baa1a1fcf24bfade (patch)
treee37eac34d78100d69ac984525f98186d1e68d0b7 /arch/arm/dts/rk3328.dtsi
parent6b26aaef083957b75bcd69aa65bd6ffcf9245bb3 (diff)
parent2454b719fb874120e06e4aa64bfb9450d091e56c (diff)
downloadu-boot-d43ef73bf26614af9b01fd57baa1a1fcf24bfade.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'arch/arm/dts/rk3328.dtsi')
-rw-r--r--arch/arm/dts/rk3328.dtsi25
1 files changed, 21 insertions, 4 deletions
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index f18cfc2627..35e02f554f 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -184,6 +184,7 @@
};
grf: syscon@ff100000 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
#address-cells = <1>;
@@ -350,6 +351,12 @@
status = "disabled";
};
+ dmc: dmc@ff400000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3328-dmc", "syscon";
+ reg = <0x0 0xff400000 0x0 0x1000>;
+ };
+
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
@@ -415,7 +422,7 @@
sdmmc: rksdmmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@@ -426,7 +433,7 @@
sdio: dwmmc@ff510000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff510000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -438,7 +445,7 @@
emmc: rksdmmc@ff520000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff520000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@@ -460,10 +467,20 @@
status = "disabled";
};
+ usb20_otg: usb@ff580000 {
+ compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff580000 0x0 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ hnp-srp-disable;
+ dr_mode = "otg";
+ status = "disabled";
+ };
+
sdmmc_ext: rksdmmc@ff5f0000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff5f0000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;