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| author | Peng Fan <van.freenix@gmail.com> | 2016-08-11 14:02:53 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-10-04 15:41:01 +0200 |
| commit | f8ca22b8de322578bc82bed224e803ca9302ee2b (patch) | |
| tree | 5321350c8c72922c3c8a50b2ab28e3f10023d3ee /arch/arm/dts/imx6ull-pinfunc-snvs.h | |
| parent | ca75159d8abc085b39e3e468ca34ccb2940d2bf5 (diff) | |
| download | u-boot-f8ca22b8de322578bc82bed224e803ca9302ee2b.tar.gz | |
arm: dts: imx6ull: add pinctrl defines
Add pinctrl defines for NXP i.MX 6ULL.
Since i.MX6ULL reuses some definitions of i.MX6UL,
also add i.MX6UL pinctrl defines from linux kernel commit (29b4817d401).
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/dts/imx6ull-pinfunc-snvs.h')
| -rw-r--r-- | arch/arm/dts/imx6ull-pinfunc-snvs.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6ull-pinfunc-snvs.h b/arch/arm/dts/imx6ull-pinfunc-snvs.h new file mode 100644 index 0000000000..da3f412e42 --- /dev/null +++ b/arch/arm/dts/imx6ull-pinfunc-snvs.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H +#define __DTS_IMX6ULL_PINFUNC_SNVS_H +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 +#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ + |