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| author | Tom Rini <trini@konsulko.com> | 2019-10-09 09:35:43 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-10-09 11:44:45 -0400 |
| commit | eaa0bde05186b1738d221bc5effc6f257a14e360 (patch) | |
| tree | 4e3c589df0fcd55fb38587ff708f6cd4a0d3863b /arch/arm/dts/imx6qdl-nitrogen6x.dtsi | |
| parent | 8c05abad1367e33908ee43c590801e338967838d (diff) | |
| parent | 9fb50c68daa696056c7842989e5f7fae1d326b34 (diff) | |
| download | u-boot-eaa0bde05186b1738d221bc5effc6f257a14e360.tar.gz | |
Merge tag 'u-boot-imx-20191009' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191009
-------------------
Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532
- MX6UL / ULZ
- Toradex board
- Allow to set OCRAM for MX6Q/D
- MX7ULP
- MX8: (container image, imx8mq_mek), SCU API
- fix several board booting from SD/EMMC (cubox-i for example)
- pico boards
[trini: display5 merged manually]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/dts/imx6qdl-nitrogen6x.dtsi')
| -rw-r--r-- | arch/arm/dts/imx6qdl-nitrogen6x.dtsi | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi new file mode 100644 index 0000000000..5094929b6d --- /dev/null +++ b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013-2019 Boundary Devices, Inc. +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include "imx6qdl-sabrelite.dtsi" + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 +#undef GP_ENET_PHY_RESET +#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 +#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Spare */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; +}; + +&fec { +#if 0 + phy-reset-gpios = GP_ENET_PHY_RESET; +#endif +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc3 { + /delete-property/ wp-gpios; +}; |