diff options
author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2019-08-15 13:57:24 +0530 |
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committer | Stefano Babic <sbabic@denx.de> | 2019-11-03 17:04:16 +0100 |
commit | 7f8a6a66af850a143c5524f703bcc726d43d43ef (patch) | |
tree | 025bf47240cae54c1bd49b8aead14cf50a14e9d2 /arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi | |
parent | 6aa874911e9fa9a594e374f80c09b766a247e255 (diff) | |
download | u-boot-7f8a6a66af850a143c5524f703bcc726d43d43ef.tar.gz |
arm: dts: Add devicetree support for iMXQXP AI_ML board
Add devicetree support for iMXQXP AI_ML board from Einfochips.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Diffstat (limited to 'arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi')
-rw-r--r-- | arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi new file mode 100644 index 0000000000..3ca53bb945 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Linaro Ltd. + */ + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; |