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| author | Laurentiu Tudor <laurentiu.tudor@nxp.com> | 2019-07-30 17:29:58 +0300 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-08-22 09:07:36 +0530 |
| commit | 5c6dc6c9a9a5f253f3928a97ca020712177884e7 (patch) | |
| tree | a389ee02cd2a589cd9f3f33db2dadec30c324c4d /arch/arm/cpu | |
| parent | aef654a2ed386d8bd53053383f6bf15ba016a79c (diff) | |
| download | u-boot-5c6dc6c9a9a5f253f3928a97ca020712177884e7.tar.gz | |
armv8: ls1088a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec. The ICID macros for SEC needed to be adapted because
the format of the registers is different.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 30 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 |
3 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index a8d3cf91fc..aa88b93175 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -47,6 +47,7 @@ endif ifneq ($(CONFIG_ARCH_LS1088A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o +obj-y += icid.o ls1088_ids.o endif ifneq ($(CONFIG_ARCH_LS1028A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c new file mode 100644 index 0000000000..956d6e78c8 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(FSL_SDMMC_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ca8005992a..72e546fad6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -340,6 +340,10 @@ void fsl_lsch3_early_init_f(void) if (fsl_check_boot_mode_secure() == 1) bypass_smmu(); #endif + +#ifdef CONFIG_ARCH_LS1088A + set_icids(); +#endif } /* Get VDD in the unit mV from voltage ID */ |