diff options
| author | Tom Warren <twarren.nvidia@gmail.com> | 2014-01-24 12:46:16 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-02-03 09:46:46 -0700 |
| commit | 2f5dac9214391efc58dc7ea5267b1322d3b18df6 (patch) | |
| tree | b1f5a0dad86f40897101736f95936ab53b78ad29 /arch/arm/cpu/tegra-common/cache.c | |
| parent | 52ef43b052964c15e051c119641d81e1f7051c14 (diff) | |
| download | u-boot-2f5dac9214391efc58dc7ea5267b1322d3b18df6.tar.gz | |
ARM: tegra: add common (shared) CPU files
These files are used by both SPL and main U-Boot.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra-common/cache.c')
| -rw-r--r-- | arch/arm/cpu/tegra-common/cache.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c index 48e9319c75..94f5bce90e 100644 --- a/arch/arm/cpu/tegra-common/cache.c +++ b/arch/arm/cpu/tegra-common/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,8 +23,6 @@ void config_cache(void) { - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; u32 reg = 0; /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ @@ -33,10 +31,10 @@ void config_cache(void) "orr r0, r0, #0x41\n" "mcr p15, 0, r0, c1, c0, 1\n"); - /* Currently, only T114 needs this L2 cache change to boot Linux */ - reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); - if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) + /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ + if (tegra_get_chip() < CHIPID_TEGRA114) return; + /* * Systems with an architectural L2 cache must not use the PL310. * Config L2CTLR here for a data RAM latency of 3 cycles. |