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authorYork Sun <york.sun@nxp.com>2016-09-13 12:40:30 -0700
committerYork Sun <york.sun@nxp.com>2016-10-06 09:56:57 -0700
commitef9a5fd8643ebdd5f492a5b09725134999f428b9 (patch)
treeaae37bebfc242c7f0f63e8e2fa3b735440deb056 /arch/arm/cpu/armv8/fsl-layerscape/mp.c
parent5d1a7a9d209fd9b8ffca1f3f27139f372a225e16 (diff)
downloadu-boot-ef9a5fd8643ebdd5f492a5b09725134999f428b9.tar.gz
armv8: fsl-layerscape: Fix "cpu status" command
The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/mp.c')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/mp.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index df7ffb88f6..f607c3900a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -104,6 +104,11 @@ int is_core_valid(unsigned int core)
return !!((1 << core) & cpu_mask());
}
+static int is_pos_valid(unsigned int pos)
+{
+ return !!((1 << pos) & cpu_pos_mask());
+}
+
int is_core_online(u64 cpu_id)
{
u64 *table;
@@ -126,9 +131,9 @@ int cpu_disable(int nr)
return 0;
}
-int core_to_pos(int nr)
+static int core_to_pos(int nr)
{
- u32 cores = cpu_mask();
+ u32 cores = cpu_pos_mask();
int i, count = 0;
if (nr == 0) {
@@ -139,14 +144,17 @@ int core_to_pos(int nr)
}
for (i = 1; i < 32; i++) {
- if (is_core_valid(i)) {
+ if (is_pos_valid(i)) {
count++;
if (count == nr)
break;
}
}
- return count;
+ if (count != nr)
+ return -1;
+
+ return i;
}
int cpu_status(int nr)