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authorPrabhakar Kushwaha <prabhakar@freescale.com>2015-11-09 16:42:07 +0530
committerYork Sun <yorksun@freescale.com>2015-11-30 08:53:04 -0800
commit449372148f6d9b5b8bded88ed8eee5c581a4bf81 (patch)
tree9e15d0812f5aebf6808e98c8d41c7a225f36b6fb /arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
parent14480454c76d0f0bc4c5828cc1f054ba6278530e (diff)
downloadu-boot-449372148f6d9b5b8bded88ed8eee5c581a4bf81.tar.gz
armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/README.lsch3')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/README.lsch34
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
index 417cf6dc24..db9359dd33 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
@@ -7,7 +7,7 @@
Freescale LayerScape with Chassis Generation 3
This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
-for example LS2085A.
+for example LS2080A.
DDR Layout
============
@@ -152,7 +152,7 @@ u-boot command
nand write <rcw image in memory> 0 <size of rcw image>
To form the NAND image, build u-boot with NAND config, for example,
-ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
nand write <u-boot image in memory> 200000 <size of u-boot image>