diff options
| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2016-06-03 18:41:31 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 14:12:50 -0700 |
| commit | b7f2bbfff6dcc2d5989bb1d20500c431f7927daf (patch) | |
| tree | 4398ed397455de7ea26c78867a1d827b1c95e0dd /arch/arm/cpu/armv8/fsl-layerscape/Makefile | |
| parent | ddd8a08052052561af38ecbe30930001a2ae940b (diff) | |
| download | u-boot-b7f2bbfff6dcc2d5989bb1d20500c431f7927daf.tar.gz | |
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/Makefile')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 5f86ef90d2..eb2cbc3f7e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -28,3 +28,7 @@ endif ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif + +ifneq ($(CONFIG_LS1012A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o +endif |