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| author | Alison Wang <alison.wang@nxp.com> | 2019-03-06 14:49:14 +0800 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-03-15 11:52:01 +0530 |
| commit | 158097052a6a528408e05d2345ff2ccdbb46036e (patch) | |
| tree | 78453d3d716aef5368b91a620203c0487fe6f378 /arch/arm/cpu/armv7/ls102xa/Kconfig | |
| parent | ba7eadd8e107202ab90d0b2937044b6dcba4b7ae (diff) | |
| download | u-boot-158097052a6a528408e05d2345ff2ccdbb46036e.tar.gz | |
armv7: ls102xa: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa/Kconfig')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 5d6a711c14..94fa68250d 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -4,6 +4,7 @@ config ARCH_LS1021A select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 + select SYS_FSL_ERRATUM_A008850 select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 @@ -63,6 +64,11 @@ config SYS_CCI400_OFFSET Offset for CCI400 base. CCI400 base addr = CCSRBAR + CCI400_OFFSET +config SYS_FSL_ERRATUM_A008850 + bool + help + Workaround for DDR erratum A008850 + config SYS_FSL_ERRATUM_A008997 bool help |